Current Issue : April - June Volume : 2011 Issue Number : 2 Articles : 8 Articles
The design of a 10-bit resistor-string digital-to-analog converter (DAC) for MOEMS micromirror interfacing is addressed in this paper. The proposed DAC, realized in a 0.18-�µm BCD technology, features a folded resistor-string stage with a switch matrix and address decoders plus an output voltage buffer stage. The proposed DAC and buffer circuitry are key elements of an innovative scanning micromirror actuator, characterized by direct digital input, full differential driving, and linear response. With respect to the the state-of-the-art resistor-string converters in similar technologies, the proposed DAC has comparable nonlinearity (INL, DNL) performances while it has the advantage of a smaller area occupation, 0.17?mm2, including output buffer, and relatively low-power consumption, 200?�µW at 500?kSPS and few �µW in idle mode....
A design of a novel bridge is proposed to interface digital-video-port (DVP) compatible image sensors with popular microcontrollers. Most commercially available CMOS image sensors send image data at high speed and in a row-by-row fashion. On the other hand, commercial microcontrollers run at relatively slower speed, and many embedded system applications need random access of pixel values. Moreover, commercial microcontrollers may not have sufficient internal memory to store a complete image of high resolution. The proposed bridge addresses these problems and provides an easy-to-use and compact way to interface image sensors with microcontrollers. The proposed design is verified in FPGA and later implemented using CMOS 0.18?um Artisan library cells. The design costs 4,735 gates and 0.12?mm2 silicon area. The synthesis results show that the bridge can support a data rate up to 254?megasamples/sec. Its applications may include pattern recognition, robotic vision, tracking system, and medical imaging....
While some leakage power reduction techniques require modification of the process technology, others are based on circuit-level optimizations and are applied at run-time. We focus our study on the latter and determine the effects of dual threshold voltage over five leakage power savings techniques: Sleep Transistor, Sleepy Stack Transistor, Sleep Keeper, LECTOR and Our Proposed technique (VSECURE).Two Input NAND gate is consider as a base case for assessment of above mentioned technique using Tanner EDA tool. In this research work effect of dual threshold voltage over static power dissipation, dynamic power dissipation and on propagation delay is experimentally observe using predictive technology 90nm models....
The coefficient values and number representations of digital FIR filters have significant impacts on the complexity of their VLSI realizations and thus on the system cost and performance. So, making a good tradeoff between implementation costs and quantization errors is essential for designing optimal FIR filters. This paper presents our complexity-aware quantization framework of FIR filters, which allows the explicit tradeoffs between the hardware complexity and quantization error to facilitate FIR filter design exploration. A new common subexpression sharing method and systematic bit-serialization are also proposed for lightweight VLSI implementations. In our experiments, the proposed framework saves 49%~51% additions of the filters with 2's complement coefficients and 10%~20% of those with conventional signed-digit representations for comparable quantization errors. Moreover, the bit-serialization can reduce 33%~35% silicon area for less timing-critical applications....
Low noise amplifier is the important block of receiver system from noise reduction point of view.This is a design procedure of Rf low noise amplifier at 2.45 GHz Frequency using CMOS technology. The main aim of this design flow & procedure was to achieve low noise figure at improved gain with the help of CMOS technology. This can become possible by using single stage nMOS transistor. The noise figure of the circuit can be kept quite low with forward voltage gain coming out to be high enough. Design has to work at low drain current with low supply voltage & biasing voltage...
The paper concentrate on implementation of VGA based Video processor. The methodology for FPGA implementing real time video processor presented in the paper aims to get high resolution. Today's display technology has found a great application with high-definition TV (HDTV), but the challenge has been to achieve high resolution, which requires faster data rates. Accelerating data rates require special image processing algorithms to support faster moving video. The industry is confronted with a major problem of implementing algorithms and getting product out market. In this paper, the installation of a hardware platform for video acquisition and restitution in real-time using a mixed software/hardware environment has been presented. The hardware platform is based on the Altera DE2 development board & Quartus-II as a software tool. Besides, it is completed with a Video source interface for acquisition and a VGA interface for restitution....
Area bloat in physical synthesis not only increases power dissipation, but also creates congestion problems, forces designers to enlarge the die area, rerun the whole design flow, and postpone the design deadline. As a result, it is vital for physical synthesis tools to achieve timing closure and low power consumption with intelligent area control. The major sources of area increase in a typical physical synthesis flow are from buffer insertion and gate sizing, both of which have been discussed extensively in the last two decades, where the main focus is individual optimized algorithm. However, building a practical physical synthesis flow\nwith buffering and gate sizing to achieve the best timing/area/runtime is rarely discussed in any previous literatures. In this paper, we present two simple yet efficient buffering and gate sizing techniques and achieve a physical synthesis flow with much smaller area bloat. Compared to a traditional timing-driven flow, our work achieves 12% logic area growth reduction, 5.8% total area reduction, 10.1% wirelength reduction, and 770 ps worst slack improvement on average on 20 industrial designs in 65nm and 45 nm....
Device mismatch and process variation models play a key role in determining the functionality and yield of sub-100?nm design. Average characteristics are often of interest, such as the average leakage current or the average read delay. However, detecting rare functional fails is critical for memory design and designers often seek techniques that enable accurately modeling such events. Extremely leaky devices can inflict functionality fails. The plurality of leaky devices on a bitline increase the dimensionality of the yield estimation problem. Simplified models are possible by adopting approximations to the underlying sum of lognormals. The implications of such approximations on tail probabilities may in turn bias the yield estimate. We review different closed form approximations and compare against the CDF matching method, which is shown to be most effective method for accurate statistical leakage modeling....
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