Current Issue : April - June Volume : 2013 Issue Number : 2 Articles : 5 Articles
In the rate-distortion optimization (RDO), the process of choosing the best prediction mode is performed through exhaustive\r\nexecutions of the whole encoding process, increasing significantly the encoder computational complexity. Considering H.264/AVC\r\nintra frame prediction, there are several modes to encode a macroblock (MB). This work proposes an algorithm and the hardware\r\ndesign for a fast intra frame mode decision module for H.264/AVC encoders. The application of the proposed algorithm reduces in\r\nmore than 10 times the number of encoding iterations for choosing the best intramode when compared with RDO-based decision.\r\nThe architecture was synthesized to FPGA and achieved an operation frequency of 98MHz processing more than 300 HD1080p\r\nframes per second. With this approach, we achieved one order-of-magnitude performance improvement compared with RDObased\r\napproaches, which is very important not only from the performance but also from the energy consumption perspective for\r\nbattery-operated devices. In order to compare the architecture with previously published works, we also synthesized it to standard\r\ncells. Compared with the best previous results reported, the implemented architecture achieves a complexity reduction of five\r\ntimes, a processing capability increase of 14 times, and a reduction in the number of clock cycles per MB of 11 times....
Side channel and fault injection attacks are major threats to cryptographic applications of embedded systems. Best performances\r\nfor these attacks are achieved by focusing sensors or injectors on the sensible parts of the application, by means of dedicated\r\nmethods to localise them. Few methods have been proposed in the past, and all of them aim at pinpointing the cryptoprocessor.\r\nHowever it could be interesting to exploit the activity of other parts of the application, in order to increase the attack�s efficiency\r\nor to bypass its countermeasures. In this paper, we present a localisation method based on cross-correlation, which issues a list\r\nof areas of interest within the attacked device. It realizes an exhaustive analysis, since it may localise any module of the device,\r\nand not only those which perform cryptographic operations. Moreover, it also does not require a preliminary knowledge about\r\nthe implementation, whereas some previous cartography methods require that the attacker could choose the cryptoprocessor\r\ninputs, which is not always possible. The method is experimentally validated using observations of the electromagnetic near field\r\ndistribution over a Xilinx Virtex 5 FPGA. The matching between areas of interest and the application layout in the FPGA floorplan\r\nis confirmed by correlation analysis....
The paper analyzes and proposes some enhancements of Ring-Oscillators-based Physical Unclonable Functions (PUFs). PUFs are\r\nused to extract a unique signature of an integrated circuit in order to authenticate a device and/or to generate a key.We show that\r\ndesigners of RO PUFs implemented in FPGAs need a precise control of placement and routing and an appropriate selection of\r\nROs pairs to get independent bits in the PUF response. We provide a method to identify which comparisons are suitable when\r\nselecting pairs of ROs. Dealing with power consumption, we propose a simple improvement that reduces the consumption of the\r\nPUF published by Suh et al. in 2007 by up to 96.6%. Last but not least, we point out that ring oscillators significantly influence one\r\nanother and can even be locked. This questions the reliability of the PUF and should be taken into account during the design....
This work describes a methodology to model power consumption of logic modules. A detailed mathematical model is presented\r\nand incorporated in a tool for translation of models written in VHDL to SystemC. The functionality for implicit power monitoring\r\nand estimation is inserted at module translation. The translation further implements an approach to wrap RTL to TLM interfaces\r\nso that the translated module can be connected to a system-level simulator. The power analysis is based on a statistical model of\r\nthe underlying HW structure and an analysis of input data. The flexibility of the C++ syntax is exploited, to integrate the power\r\nevaluation technique. The accuracy and speed-up of the approach are illustrated and compared to a conventional power analysis\r\nflow using PPR simulation, based on Xilinx technology....
We propose an FPGA design for the relevancy computation part of a high-throughput real-time search application. The application\r\nmatches terms in a stream of documents against a static profile, held in off-chip memory. We present a mathematical analysis of\r\nthe throughput of the application and apply it to the problem of scaling the Bloom filter used to discard nonmatches....
Loading....