Current Issue : April - June Volume : 2014 Issue Number : 2 Articles : 5 Articles
We propose a new Polygonal Field Programmable Gate Array (PFPGA) that consists of many logic blocks interconnected by a\r\ngeneric three-stage three-sided rearrangeable polygonal switching network (PSN). The main component of this PSN consists of\r\na polygonal switch block interconnected by crossbars. In comparing our PSN with a three-stage three-sided clique-based (Xilinx\r\n4000-like FPGAs) (Palczewski; 1992) switching network of the same size and with the same number of switches, we find that the\r\nthree-stage three-sided clique-based switching network is not rearrangeable. Also, the effects of the rearrangeable structure and\r\nthe number of terminals on the network switch-efficiency are explored and a proper set of parameters is determined to minimize\r\nthe number of switches. Moreover, we explore the effect of the PSN structure and granularity of cluster logic blocks on the switch\r\nefficiency of PFPGA. Experiments on benchmark circuits show that switches and speed performance are significantly improved.\r\nBased on experiment results, we can determine the parameters of PFPGA for the VLSI implementation....
Embedded systems are widely used today in different digital signal processing (DSP) applications that usually require high\r\ncomputation power and tight constraints. The design space to be explored depends on the application domain and the target\r\nplatform. A tool that helps explore different architectures is required to design such an efficient system. This paper proposes an\r\narchitecture exploration framework forDSP applications based on Particle SwarmOptimization (PSO) and genetic algorithms (GA)\r\ntechniques that can handle multiobjective optimization problems with several hybrid forms. A novel approach for performance\r\nevaluation of embedded systems is also presented. Several cycle-accurate simulations are performed for commercial embedded\r\nprocessors. These simulation results are used to build an artificial neural network (ANN)model that can predict performance/power\r\nof newly generated architectures with an accuracy of 90% compared to cycle-accurate simulations with a very significant time\r\nsaving. Thesemodels are combined with an analyticalmodel and static scheduler to further increase the accuracy of the estimation\r\nprocess.The functionality of the framework is verified based on benchmarks provided by our industrial partnerONSemiconductor\r\nto illustrate the ability of the framework to investigate the design space...
This paper examines fault tolerant adder designs implemented on FPGAs which are inspired by the methods of modular\r\nredundancy, roving, and gradual degradation. A parallel-prefix adder based upon the Kogge-Stone configuration is compared with\r\nthe simple ripple carry adder (RCA) design. The Kogge-Stone design utilizes a sparse carry tree complemented by several smaller\r\nRCAs. Additional RCAs are inserted into the design to allow fault tolerance to be achieved using the established methods of roving\r\nand gradual degradation. A triple modular redundant ripple carry adder (TMR-RCA) is used as a point of reference. Simulation\r\nand experimental measurements on a Xilinx Spartan 3E FPGA platform are carried out. The TMR-RCA is found to have the best\r\ndelay performance and most efficient resource utilization for an FPGA fault-tolerant implementation due to the simplicity of the\r\napproach and the use of the fast-carry chain. However, the superior performance of the carry-tree adder over an RCA in a VLSI\r\nimplementation makes this proposed approach attractive for ASIC designs....
This paper considers the problem of scheduling a chain of n coarse-grained tasks on a linear array of k reconfigurable FPGAs\r\nwith the objective of primarily minimizing reconfiguration time. A high-level meta-algorithm along with two detailed metaalgorithms\r\n(GPRM and SPRM) that support a wide range of problem formulations and cost functions is presented. GPRM, themore\r\ngeneral of the two schemes, reduces the problem to computing a shortest path in a DAG; SPRM, the less general scheme, employs\r\ndynamic programming. Both meta algorithms are linear in n and compute optimal solutions. GPRMcan be exponential in k but is\r\nnevertheless practical because k is typically a small constant.The deterministic quality of this meta algorithm and the guarantee of\r\noptimal solutions for all of the formulations discussed make this approach a powerful alternative to other metatechniques such as\r\nsimulated annealing and genetic algorithms....
In this paper it is propose a broadband low noise amplifier with high linearity performance. The amplifier achieves broadband, low noise performance and high linearity using a bias circuit with high impedance. The bias circuit consists of an inductor, a resistor, and a current source. The circuit obtains high impedance using a high resistive component. It is also propose a broadband, frequency-selective low-noise amplifier (LNA) with at least 25 dB of rejection at frequencies below the L-band (includes GPS and GSM carriers) is fabricated in a 90 nm standard CMOS process and the proposed LNA can be used for broadband impulse-radio ultra-wideband (IR-UWB) and frequency modulated FM-UWB....
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