Current Issue : July - September Volume : 2014 Issue Number : 3 Articles : 6 Articles
Many applications ranging from machine learning, image processing, and machine vision to optimization utilize matrix\nmultiplication as a fundamental block. Matrix operations play an important role in determining the performance of such\napplications. This paper proposes a novel efficient, highly scalable hardware accelerator that is of equivalent performance to\na 2GHz quad core PC but can be used in low-power applications targeting embedded systems requiring high performance\ncomputation. Power, performance, and resource consumption are demonstrated on a fully-functional prototype. The proposed\nhardware accelerator is 36Ã?â?? more energy efficient per unit of computation compared to state-of-the-art Xeon processor of equal\nvintage and is 14Ã?â?? more efficient as a stand-alone platform with equivalent performance. An important comparison between\nsimulated system estimates and real system performance is carried out....
Data retention and leakage current reduction are among the major area of concern in today’s CMOS technology. A static random access memory (SRAM) is designed to plug two needs: i) The SRAM provides as cache memory, stuck between central processing unit and Dynamic Random Access Memory (DRAM). ii) The SRAM technology act as driving force for low power application since SRAM is portable compared to DRAM and SRAM doesn't have need of any refresh current. Advancement of technology greatly affects the leakage current and leakage power of SRAM cell. Leakage current in memory cell is dominating factor, which is mainly impinge on the power consumption. In this paper, we've illustrated the design and implementation of FINFET based 4 x 4 SRAM cell array by means of one bit 6T SRAM. It has been carried out via FINFET HSPICE modeling with read and write procedure of SRAM memory....
Logarithmic number system (LNS) is an attractive alternative to realize finite-length impulse response filters because of\nmultiplication in the linear domain being only addition in the logarithmic domain. In the literature, linear coefficients are directly\nreplaced by the logarithmic equivalent. In this paper, an approach to directly optimize the finite word length coefficients in the\nLNS domain is proposed. This branch and bound algorithm is implemented based on LNS integers and several different branching\nstrategies are proposed and evaluated. Optimal coefficients in the minimax sense are obtained and compared with the traditional\nfinite word length representation in the linear domain as well as using rounding. Results show that the proposed method naturally\nprovides smaller approximation error compared to rounding. Furthermore, they provide insights into finite word length properties\nof FIR filters coefficients in the LNS domain and show that LNS FIR filters typically provide a better approximation error compared\nto a standard FIR filter....
A novel quantization error (QE) compensation method is proposed in design of high accuracy fixed-width radix-4 Booth\nmultipliers, which will effectively reduce the QE and save the area of multipliers when they are employed in cognitive radio (CR)\ndetector and digital signal processor (DSP).The truncated partial-products of the proposedmultipliers are finely divided into three\nsections: reserved section, adaptive compensation section, and constant compensation section.TheQE compensation carries of the\nmultipliers are generated by applying probability estimation based on a shrunken minor truncated sectionwhich is a combination of\nthe constant compensation and adaptive compensation. The proposed compensation method not only reduces the QE of the fixedwidth\nBooth multipliers, but also avoids the exhaustive computing resources (time and memory) during getting the compensation\ncarries by statistical simulation.The proposed method can achieve higher accuracy than the existing works under the same area and\npower budgets. Simulation and experiment results show that the improved compensation method has the minimum power-delay\nproducts compared with the existingmethods under the same area and can save up to 30% area for realization of full-width radix-4\nBooth multipliers....
For a design to survive unforeseen physical effects like aging, temperature variation, and/or emergence of new application\nstandards, adaptability needs to be supported. Adaptability, in its complete strength, is present in reconfigurable processors,\nwhich makes it an important IP in modern System-on-Chips (SoCs). Reconfigurable processors have risen to prominence as\na dominant computing platform across embedded, general-purpose, and high-performance application domains during the last\ndecade. Significant advances have been made in many areas such as, identifying the advantages of reconfigurable platforms, their\nmodeling, implementation flow and finally towards early commercial acceptance. This paper reviews these progresses fromvarious\nperspectives with particular emphasis on fundamental challenges and their solutions. Empowered with the analysis of past, the\nfuture research roadmap is proposed....
In the past few years reversible logic is very promising research area and has applications in several technologies like nano-electronics, low power CMOS design, optical computing, bioinformatics, quantum computing. Nowadays reversible logic gates are emerging to be compatible with future generation technology which has significant reduction in overall heat dissipation. FPGAs are more demanding in recent years due to its features of changing design up to last minute and it provides ability for designers to avoid pitfall of nano-electronic design. But the area and power consumption is major drawback of FPGAs over application specific ICs (ASICs). In this manuscript our approach is towards design and implementation of logic block of Plessey FPGAs with reduced number reversible gates, quantum cost and garbage output. Our proposed design is based on most cost effective reversible circuit including 3*3 MUX gate (MG) in comparison with existing reversible circuit in literature....
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