Current Issue : October - December Volume : 2014 Issue Number : 4 Articles : 4 Articles
We introduce a dynamically reconfigurable 2D filterbank that supports both real and complex-valued inputs, outputs, and filter coefficients. This general purpose filterbank allows for the efficient implementation of 2D filterbanks based on separable 2D FIR filters that support all possible combinations of input and output signals. The system relies on the use of dynamic reconfiguration of real/complex one-dimensional filters to minimize the required hardware resources. The system is demonstrated using an equiripple and a Gabor filterbank and the results using both real and complex-valued input images. We summarize the performance of the system in terms of the required processing times, energy, and accuracy....
Offshore fabrication, assembling and packaging challenge chip security, as original chip designs may be tampered by malicious\ninsertions, known as hardware Trojans (HTs).HTdetection is imperative to guarantee the chip performance and safety. ExistingHT\ndetection methods have limited capability to detect small-scale HTs and are further challenged by the increased process variation.\nTo increase HT detection sensitivity and reduce chip authorization time, we propose to exploit the inherent feature of differential\ncascade voltage switch logic (DCVSL) to detect HTs at runtime. In normal operation, a system implemented with DCVSL always\nproduces complementary logic values in internal nets and final outputs. Noncomplementary values on inputs and internal nets in\nDCVSL systems potentially result in abnormal power behavior and even system failures. By examining special power characteristics\nof DCVSL systems upon HT insertion, we can detect HTs, even if the HT size is small. Simulation results show that the proposed\nmethod achieves up to 100% HT detection rate. The evaluation on ISCAS benchmark circuits shows that the proposed method\nobtains a HT detection rate in the range of 66% to 98%....
In chip-multiprocessors (CMP) architecture, the L2 cache is shared by the L1 cache of each processor core, resulting in a high\nvolume of diverse data transfer through the L1-L2 cache bus. High-performance CMP and SoC systems have a significant amount\nof data transfer between the on-chip L2 cache and the L3 cache of off-chip memory through the power expensive off-chip memory\nbus. This paper addresses the problem of the high-power consumption of the on-chip data buses, exploring a framework for\nmemory data bus power consumption minimization approach. A comprehensive analysis of the existing bus power minimization\napproaches is provided based on the performance, power, and area overhead consideration. A novel approaches for reducing the\npower consumption for the on-chip bus is introduced. In particular, a serialization-widening (SW) of data bus with frequent value\nencoding (FVE), called the SWE approach, is proposed as the best power savings approach for the on-chip cache data bus. The\nexperimental results show that the SWE approach with FVE can achieve approximately 54% power savings over the conventional\nbus for multicore applications using a 64-bit wide data bus in 45 nm technology....
This paper describes an embedded FFT processor where the higher radices butterflies maintain one complexmultiplier in its critical\npath. Based on the concept of a radix-r fast Fourier factorization and based on the FFT parallel processing, we introduce a new\nconcept of a radix-r Fast Fourier Transform in which the concept of the radix-r butterfly computation has been formulated as the\ncombination of radix-2????/4???? butterflies implemented in parallel. By doing so, the VLSI butterfly implementation for higher radices\nwould be feasible since itmaintains approximately the same complexity of the radix-2/4 butterflywhich is obtained by block building\nof the radix-2/4 modules. The block building process is achieved by duplicating the block circuit diagram of the radix-2/4 module\nthat is materialized by means of a feed-back network which will reuse the block circuit diagram of the radix-2/4 module....
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