Current Issue : January - March Volume : 2014 Issue Number : 1 Articles : 4 Articles
Current software-based packet classification algorithms exhibit relatively poor performance, prompting many researchers to\r\nconcentrate on novel frameworks and architectures that employ both hardware and software components.ThePacket Classification\r\nwith Incremental Update (PCIU) algorithm, Ahmed et al. (2010), is a novel and efficient packet classification algorithm with a\r\nunique incremental update capability that demonstrated excellent results and was shown to be scalable for many different tasks and\r\nclients. While a pure software implementation can generate powerful results on a server machine, an embedded solution may be\r\nmore desirable for some applications and clients. Embedded, specialized hardware accelerator based solutions are typically much\r\nmore efficient in speed, cost, and size than solutions that are implemented on general-purpose processor systems. This paper seeks\r\nto explore the design space of translating the PCIU algorithm into hardware by utilizing several optimization techniques, ranging\r\nfrom fine grain to coarse grain and parallel coarse grain approaches.The paper presents a detailed implementation of a hardware\r\naccelerator of the PCIU based on an Electronic System Level (ESL) approach. Results obtained indicate that the hardware accelerator\r\nachieves on average 27x speedup over a state-of-the-art Xeon processor....
This paper presents a novel implementation of the JPEG2000 standard as a system on a chip (SoC). While most of the research\r\nin this field centers on acceleration of the EBCOT Tier I encoder, this work focuses on an embedded solution for EBCOT Tier II.\r\nSpecifically, this paper proposes using an embedded softcore processor to performTier II processing as the back end of an encoding\r\npipeline.TheAlteraNIOS II processor is chosen for the implementation and is coupled with existing embedded processingmodules\r\nto realize a fully embedded JPEG2000 encoder.The design is synthesized on a Stratix IV FPGA and is shown to out perform other\r\ncomparable SoC implementations by 39% in computation time....
In this paper, we present a technique to maximize the lifetime of SRAM-based FPGAs in space mission. We focus on recovering\r\npermanent faults induced by SEE (single-events effect). In our technique, we use a fix-sized fault detection module to detect\r\npermanent faults and propose a permanent fault recovery mechanism for fault recovery. By using partial reconfiguration,we develop\r\na system lifetime estimation model to find the optimal partition for designing the module-based fault recovering with the maximum\r\nsystem lifetime.We conduct experiments with a set of real applications including SpaceWire, Wavelet, AC97, MEPG-4, 8086, and\r\nEthernet on Xilinx XUP platforms. The experimental results show our technique can effectively improve the lifetime compared\r\nwith the previous work....
The emergence of mobile and battery operated multimedia systems and the diversity of supported applications mount new\r\nchallenges in terms of design efficiency of these systems which must provide a maximum application quality of service (QoS)\r\nin the presence of a dynamically varying environment. These optimization problems cannot be entirely solved at design time and\r\nsome efficiency gains can be obtained at run-time by means of self-adaptivity. In this paper, we propose a new cross-layer hardware\r\n(HW)/software (SW) adaptation solution for embedded mobile systems. It supports application QoS under real-time and lifetime\r\nconstraints via coordinated adaptation in the hardware, operating system (OS), and application layers. Our method relies on an\r\noriginal middleware solution used on both global and local managers.The global manager (GM) handles large, long-termvariations\r\nwhereas the local manager (LM) is used to guarantee real-time constraints. The GM acts in three layers whereas the LM acts in\r\napplication and OS layers only.The main role of GMis to select the best configuration for each application to meet the constraints\r\nof the system and respect the preferences of the user. The proposed approach has been applied to a 3D graphics application and\r\nsuccessfully implemented on an Altera FPGA....
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