Current Issue : April - June Volume : 2014 Issue Number : 2 Articles : 4 Articles
Multi-FPGA hardware prototyping is becoming increasingly important in the system on chip design cycle. However, after\r\npartitioning the design on the multi-FPGA platform, the number of inter-FPGA signals is greater than the number of physical\r\nconnections available on the prototyping board. Therefore, these signals should be time-multiplexed which lowers the system\r\nfrequency. The way in which the design is partitioned affects the number of inter-FPGA signals. In this work, we propose a set\r\nof constraints to be taken into account during the partitioning task. Then, the resulting inter-FPGA signals are routed with an\r\niterative routing algorithm in order to obtain the best multiplexing ratio. Indeed, signals are grouped and then routed using the\r\nintra-FPGA routing algorithm: Pathfinder. This algorithm is adapted to deal with the inter-FPGA routing problem.Many scenarios\r\nare proposed to obtain the most optimized results in terms of prototyping system frequency. Using this technique, the system\r\nfrequency is improved by an average of 12.8% compared to constructive routing algorithm....
The wave dynamic differential logic (WDDL) has been identified as a promising countermeasure to increase the robustness of\r\ncryptographic devices against differential power attacks (DPA). However, to guarantee the effectiveness of WDDL technique, the\r\nrouting in both the direct and complementary paths must be balanced. This paper tackles the problem of unbalance of dual-rail\r\nsignals in WDDL design.We describe placement techniques suitable for tree-based and mesh-based FPGAs and quantify the gain\r\nthey confer. Then, we introduce a timing-balance-driven routing algorithm which is architecture independent. Our placement\r\nand routing techniques proved to be very promising. In fact, they achieve a gain of 95%, 93%, and 85% in delay balance in treebased,\r\nsimple mesh, and cluster-based mesh architectures, respectively. To reduce further the switch and delay unbalance in Mesh\r\narchitecture, we propose a differential pair routing algorithm that is specific to cluster-based mesh architecture. It achieves perfectly\r\nbalanced routed signals in terms of wire length and switch number....
Intellectual property (IP) core based design is an emerging design methodology to deal with increasing chip design complexity.\r\nC/C++ based high level synthesis (HLS) is also gaining traction as a design methodology to deal with increasing design complexity.\r\nIn the work presented here, we present a design methodology that combines these two individual methodologies and is therefore\r\nmore powerful. We discuss our proposed methodology in the context of supporting efficient hardware synthesis of a class of\r\nmathematical functions without altering original C/C++ source code. Additionally, we also discuss and propose methods to\r\nintegrate legacy IP cores in existing HLS flows. Relying on concepts from the domains of program recognition and optimized\r\nlow level implementations of such arithmetic functions, the described design methodology is a step towards intelligent synthesis\r\nwhere application characteristics arematched with specific architectural resources and relevant IP cores in a transparent manner for\r\nimproved area-delay results. The combined methodology is more aware of the target hardware architecture than the conventional\r\nHLS flow. Implementation results of certain compute kernels froma commercial tool Vivado-HLS as well as proposed flow are also\r\ncompared to show that proposed flow gives better results....
The potential of FPGAs as accelerators for high-performance computing applications is very large, but many factors are involved\r\nin their performance.The design for FPGAs and the selection of the proper optimizations when mapping computations to FPGAs\r\nlead to prohibitively long developing time. Alternatives are the high-level synthesis (HLS) tools, which promise a fast design\r\nspace exploration due to design at high-level or analytical performance models which provide realistic performance expectations,\r\npotential impediments to performance, and optimization guidelines. In this paper we propose the combination of both, in order\r\nto construct a performance model for FPGAs which is able to visually condense all the helpful information for the designer. Our\r\nproposed model extends the roofline model, by considering the resource consumption and the parameters used in the HLS tools,\r\nto maximize the performance and the resource utilization within the area of the FPGA. The proposed model is applied to optimize\r\nthe design exploration of a class of window-based image processing applications using two different HLS tools. The results show\r\nthe accuracy of the model as well as its flexibility to be combined with any HLS tool....
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