Current Issue : January - March Volume : 2015 Issue Number : 1 Articles : 7 Articles
In network-on-chip (NoC), the data transferring by virtual channels can avoid the issue of data loss and deadlock. Many virtual\nchannels on one input or output port in router are included. However, the router includes five I/O ports, and then the power\nissue is very important in virtual channels. In this paper, a novel architecture, namely, Smart Power-Saving (SPS), for low power\nconsumption and low area in virtual channels of NoC is proposed. The SPS architecture can accord different environmental factors\nto dynamically save power and optimization area in NoC. Comparison with related works, the new proposed method reduces\n37.31%, 45.79%, and 19.26% on power consumption and reduces 49.4%, 25.5% and 14.4% on area, respectively....
An engineering change orders design using multiple variable linear programming for VLSI design is presented in this paper. This\napproach addresses themain issues of resource between spare cells and target cells.We adopt linear programming technique to plan\nand balance the spare cells and target cells to meet the new specification according to logic transformation.The proposed method\nsolves the related problem of resource for ECO problems and provides a well solution. The scheme shows new concept to manage\nthe spare cells to meet possible target cells for ECO research...
Circuit reliability has become a growing concern in today�s nanoelectronics, which motivates strong research interest over the\nyears in reliability analysis and reliability-oriented circuit design. While quite a few approaches for circuit reliability analysis have\nbeen reported, there is a lack of comparative studies on their pros and cons in terms of both accuracy and efficiency. This paper\nprovides an overview of some typical methods for reliability analysis with focus on gate-level circuits, large or small, with or without\nreconvergent fanouts. It is intended to help the readers gain an insight into the reliability issues, and their complexity as well as\noptional solutions.Understanding the reliability analysis is also a first step towards advanced circuit designs for improved reliability\nin the future research....
This paper presents a new multioutput and high throughput pseudorandom number generator. The scheme is to make the\nhomogenized Logistic chaotic sequence as unified hyperchaotic system parameter. So the unified hyperchaos can transfer in\ndifferent chaotic systems and the output can be more complex with the changing of homogenized Logistic chaotic output.\nThrough processing the unified hyperchaotic 4-way outputs, the output will be extended to 26 channels. In addition, the generated\npseudorandomsequences have all passed NIST SP800-22 standard test and DIEHARD test. The system is designed in Verilog HDL\nand experimentally verified on a Xilinx Spartan 6 FPGA for a maximum throughput of 16.91Gbits/s for the native chaotic output\nand 13.49Gbits/s for the resulting pseudorandom number generators....
New ternary adders, which are fundamental components of ternary addition, are presented in this paper. They are on the basis\nof a logic style which mostly generates binary signals. Therefore, static power dissipation reaches its minimum extent. Extensive\ndifferent analyses are carried out to examine how efficient the new designs are. For instance, the ternary ripple adder constructed by\nthe proposed ternary half and full adders consumes 2.33 ????Wless power than the one implemented by the previous adder cells. It is\nalmost twice faster as well. Due to their unique superior characteristics for ternary circuitry, carbon nanotube field-effect transistors\nare used to form the novel circuits, which are entirely suitable for practical applications....
We are going to design and simulate low power fractional-N phase-locked loop (FNPLL) frequency synthesizer for industrial\napplication, which is based on VLSI. The design of FNPLL has been optimized using different VLSI techniques to acquire\nsignificant performance in terms of speed with relatively less power consumption. One of the major contributions in optimization\nis contributed by the loop filter as it limits the switching time between cycles. Sigma-delta modulator attenuates the noise generated\nby the loop filter. This paper presents the implementation details and simulation results of all the blocks of optimized design....
Design strategies for parallel iterative algorithms are presented. In order to further study different tradeoff strategies in design\ncriteria for integrated circuits, A 10 Ã?â?? 10 Jacobi Brent-Luk-EVD array with the simplified ????-CORDIC processor is used as an\nexample.Thee xperimental results show that using the ????-CORDIC processor is beneficial for the design criteria as it yields a smaller\narea, faster overall computation time, and less energy consumption than the regular CORDIC processor. It is worth to notice that\nthe proposed parallel EVD method can be applied to real-time and low-power array signal processing algorithms performing\nbeamforming or DOA estimation....
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