Current Issue : January - March Volume : 2015 Issue Number : 1 Articles : 4 Articles
This paper presents an efficient all digital carrier recovery loop (ADCRL) for quadrature phase shift keying (QPSK). The ADCRL\ncombines classic closed-loop carrier recovery circuit, all digital Costas loop (ADCOL), with frequency feedward loop, maximum\nlikelihood frequency estimator (MLFE) so as to make the best use of the advantages of the two types of carrier recovery loops and\nobtain amore robust performance in the procedure of carrier recovery. Besides, considering that, for MLFE, the accurate estimation\nof frequency offset is associated with the linear characteristic of its frequency discriminator (FD), the Coordinate Rotation Digital\nComputer (CORDIC) algorithm is introduced into the FDbased on MLFE to unwrap linearly phase difference.The frequency offset\ncontained within the phase difference unwrapped is estimated by the MLFE implemented just using some shifter and multiplyaccumulate\nunits to assist the ADCOL to lock quickly and precisely. The joint simulation results ofModelSim andMATLAB show\nthat the performances of the proposed ADCRL in locked-in time and range are superior to those of the ADCOL. On the other\nhand, a systematic design procedure based on FPGA for the proposed ADCRL is also presented...
The enumeration of two-dimensional Costas arrays is a problem with factorial time complexity and has been solved for sizes up to\n29 using computer clusters. Costas arrays of higher dimensionality have recently been proposed and their properties are beginning\nto be understood. This paper presents, to the best of our knowledge, the first proposed implementations for enumerating these\nmultidimensional arrays in GPUs and FPGAs, as well as the first discussion of techniques to prune the search space and reduce\nenumeration run time. Both GPU and FPGA implementations rely on Costas array symmetries to reduce the search space and\nperform concurrent explorations over the remaining candidate solutions. The fine grained parallelism utilized to evaluate and\nprogress the exploration, coupled with the additional concurrency provided by the multiple instanced cores, allowed the FPGA\n(XC5VLX330-2) implementation to achieve speedups of up to 30Ã?â?? over the GPU (GeForce GTX 580)....
This paper describes a novel way to exploit the computation capabilities delivered by modern Field-Programmable Gate Arrays\n(FPGAs), not only towards a higher performance, but also towards an improved reliability. Computation-specific pieces of circuitry\nare dynamically scheduled and allocated to different resources on the chip based on a set of novel algorithms which are described\nin detail in this article. These algorithms consider most of the technological constraints existing inmodern partially reconfigurable\nFPGAs as well as spontaneously occurring faults and emerging permanent damage in the silicon substrate of the chip. In addition,\nthe algorithms target other important aspects such as communications and synchronization among the different computations that\nare carried out, either concurrently or at different times. The effectiveness of the proposed algorithms is tested by means of a wide\nrange of synthetic simulations, and, notably, a proof-of-concept implementation of them using real FPGA hardware is outlined....
The Internet architecture works well for a wide variety of communication scenarios. However, its flexibility is limited because\nit was initially designed to provide communication links between a few static nodes in a homogeneous network and did not\nattempt to solve the challenges of today�s dynamic network environments. Although the Internet has evolved to a global system of\ninterconnected computer networks, which links together billions of heterogeneous compute nodes, its static architecture remained\nmore or less the same. Nowadays the diversity in networked devices, communication requirements, and network conditions vary\nheavily, which makes it difficult for a static set of protocols to provide the required functionality. Therefore, we propose a self aware\nnetwork architecture in which protocol stacks can be built dynamically. Those protocol stacks can be optimized continuously\nduring communication according to the current requirements. For this network architecture we propose an FPGA-based execution\nenvironment called Embed Net that allows for a dynamic mapping of network protocols to either hardware or software. We show\nthat our architecture can reduce the communication overhead significantly by adapting the protocol stack and that the dynamic\nhardware/software mapping of protocols considerably reduces the CPU load introduced by packet processing....
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