Current Issue : April - June Volume : 2015 Issue Number : 2 Articles : 4 Articles
Complexity in processor micro architecture and the related issues of power density, hot spots and wire delay, are seen to be a major\nconcern for design migration into low nano meter technologies of the future. This paper evaluates the hardware cost of an alternative\nto register-file organization, the super scalar stack issue array (SSIA).We believe this is the first such reported study using discrete\nstack elements. Several possible implementations are evaluated, using a 90 nm standard cell library as a reference model, yielding\ndelay data and FO4 metrics. The evaluation, including reference to ASIC layout, RC extraction, and timing simulation, suggests a\n4-wide issue rate of at least four Giga-ops/sec at 90nm and opportunities for twofold future improvement by using more advanced\ndesign approaches....
Multiplication is one of the most commonly used operations in the arithmetic.Multipliers based on Wallace reduction tree provide\nan area-efficient strategy for high speed multiplication. A number of modifications are proposed in the literature to optimize the\narea of the Wallace multiplier.This paper proposed a reduced-area Wallace multiplier without compromising on the speed of the\noriginal Wallace multiplier.Designs are synthesized using Synopsys Design Compiler in 90 nm process technology. Synthesis results\nshow that the proposed multiplier has the lowest area as compared to other tree-based multipliers. The speed of the proposed and\nreference multipliers is almost the same....
We propose an approach to design of an algebraic signature analyzer that can be used for mixed-signal systems testing.The analyzer\ndoes not contain carry propagating circuitry, which improves its performance as well as fault tolerance. The common design\ntechnique of a signature analyzer for mixed-signal systems is based on the rules of an arithmetic finite field.The application of this\ntechnique to the systems with an arbitrary radix is a challenging task and the devices designed possess high hardware complexity.\nThe proposed technique is simple and applicable to systems of any size and radix. The hardware complexity is low. The technique\ncan also be used in arithmetic/algebraic coding and cryptography....
Embedded systems include an increasing share of analog/mixed-signal components that are tightly interwoven with functionality\nof digital HW/SW systems. A challenge for verification is that even small deviations in analog components can lead to significant\nchanges in system properties. In this paper we propose the combination of range-based, semisymbolic simulation with assertion\nchecking. We show that this approach combines advantages, but as well some limitations, of multirun simulations with formal\ntechniques. The efficiency of the proposed method is demonstrated by several examples....
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