Current Issue : July - September Volume : 2015 Issue Number : 3 Articles : 4 Articles
Being an essential part of infrared readout integrated circuit, correlated double sampling (CDS) circuits play important roles in both\ndepressing reset noise and conditioning integration signals. To adapt applications for focal planes of large format and high density,\na new structure of CDS circuit occupying small layout area is proposed, whose power dissipation has been optimized by using\nMOSFETs in operation of subthreshold region, which leads to 720 nW. Then the noise calculation model is established, based on\nwhich the noise analysis has been carried out by the approaches of transfer function and numerical simulations using SIMULINK\nand Verilog-A. The results are in good agreement, demonstrating the validity of the present noise calculation model. Thermal noise\nplays a dominant role in the long wave situation while 1/f noise is themajority in the medium wave situation. The total noise of\nlong wave is smaller than medium wave, both of which increase with the integration capacitor and integration time increasing....
According to the problems of current distributed architecture intrusion detection systems (DIDS), a new online distributed\nintrusion detection model based on cellular neural network (CNN) was proposed, in which discrete-time CNN (DTCNN) was\nused as weak classifier in each local node and state-controlled CNN (SCCNN) was used as global detection method, respectively.\nWe further proposed a new method for design template parameters of SCCNN via solving Linear Matrix Inequality. Experimental\nresults based on KDDCUP 99 dataset show its feasibility and effectiveness. Emerging evidence has indicated that this new approach\nis affordable to parallelism and analog very large scale integration (VLSI) implementation which allows the distributed intrusion\ndetection to be performed better....
The current status of High K dielectrics in Very Large Scale Integrated circuit\n(VLSI) manufacturing for leading edge Dynamic Random Access Memory (DRAM) and\nComplementary Metal Oxide Semiconductor (CMOS) applications is summarized along\nwith the deposition methods and general equipment types employed. Emerging applications\nfor High K dielectrics in future CMOS are described as well for implementations in 10 nm and\nbeyond nodes. Additional emerging applications for High K dielectrics include Resistive\nRAM memories, Metal-Insulator-Metal (MIM) diodes, Ferroelectric logic and memory\ndevices, and as mask layers for patterning. Atomic Layer Deposition (ALD) is a common and\nproven deposition method for all of the applications discussed for use in future\nVLSI manufacturing....
Achieving good detection performance while\nincurring low complexity is known to be one of\nthe major challenges in multiple-input multiple-output\n(MIMO) communications based on spatial multiplexing.\nThe tuple search detector (TSD) was recently introduced,\nimproving this trade-off with regard to other\ntree-search-based algorithms (e.g. single tree search or\nlist sphere detector). Motivated by the tremendous gain\nachievable through the turbo principle and based on a\npreviously developed soft-output (SO) TSD implementation,\nthis work presents the first soft-input soft-output\n(SISO) TSD realization, scalable in constellation size\nand number of antennas and mapped to a highly parallel\nand pipelined VLSI architecture. The proposed\nSISO-TSD VLSI realization is instantiated for 4 Ã?â?? 4\nMIMO transmission and 64-QAM constellation in 65-\nnm CMOS technology. For a given BER?complexity\ntrade-off, the throughput ranges from 57.3 Mbps (iterative\ndetection-decoding with 3 iterations) to 403.6\nMbps (non-iterative detection-decoding) at a clock frequency\nof 454 MHz. The BER?complexity trade-off\ncan be moreover adjusted according to transmission\nconditions, reaching >1 Gbps in high SNR scenarios.\nA silicon area of 0.14 mm2 (97.7 kGEs) is occupied\nby the SISO-TSD core, reporting low power dissipation\n(58.2 mW ââ?¬â?? 73.9 mW) under typical case operat ing conditions. The proposed detector implementation\nachieves hence high throughput with reasonable hardware\ncomplexity, representing a very competitive strategy\nwith regard to relevant state-of-the-art realizations....
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