Current Issue : October - December Volume : 2015 Issue Number : 4 Articles : 4 Articles
The pursuit of continuous scaling of electronic devices in the semiconductor\nindustry has led to two unintended but significant outcomes: a rapid increase in susceptibility\nto radiation induced errors, and an overall rise in power consumption. Operating under\nlow voltage to reduce power only aggravates radiation related reliability issues. The\nproposed ââ?¬Å?SEU Hardening Incorporating Extreme Low Power Bitcell Designââ?¬Â (SHIELD)\naddresses these two major concerns simultaneously. It is based on the concept of gating\nthe conventional cross-coupled inverters while introducing a novel ââ?¬Å?cut-offââ?¬Â network.\nThis creates redundant storage nodes and eliminates the internal feedback loop during\nradiation particle impact. The SHIELD bitcell tolerates upsets with charge deposits over\n1 pC. Simulations confirm its advantages in terms of leakage power, with more than twofold\nlower leakage currents than previous solutions when operated at a 700mV supply voltage in\na 65 nm process. To validate the bitcellââ?¬â?¢s robustness, several test cases and special concerns,\nincluding multiple node upsets (MNU) and half-select, are examined....
This paper proposes a review of several circuits for communication and wireless\nsensing applications implemented on cellulose-based materials. These circuits have been\ndeveloped during the last years exploiting the adhesive copper laminate method. Such a\ntechnique relies on a copper adhesive tape that is shaped by a photo-lithographic process\nand then transferred to the hosting substrate (i.e., paper) by means of a sacrificial layer.\nThe presented circuits span from UHF oscillators to a mixer working at 24 GHz and\nconstitute an almost complete set of building blocks that can be applied to a huge variety\ncommunication apparatuses. Each circuit is validated experimentally showing performance\ncomparable with the state-of-the-art. This paper demonstrates that circuits on cellulose are\ncapable of operating at record frequencies and that ultra- low cost, green i.e., recyclable and\nbiodegradable) materials can be a viable solution to realize high frequency hardware for the\nupcoming Internet of Things (IoT) era....
In this study, we demonstrate near-0.1 V minimum operating voltage of a\nlow-variability Silicon on Thin Buried Oxide (SOTB) process for one million logic gates\non silicon. Low process variability is required to obtain higher energy efficiency during\nultra-low-voltage operation with steeper subthreshold slope transistors. In this study,\nwe verify the decrease in operating voltage of logic circuits via a variability-suppressed\nSOTB process. In our measurement results with test chips fabricated in 65-nm SOTB and\nbulk processes, the operating voltage at which the first failure is observed was lowered\nfrom 0.2 to 0.125 V by introducing a low-variability SOTB process. Even at 0.115 V,\nover 40% yield can be expected as per our measurement results on SOTB test chips....
In this paper, we analyze the variability of III-V homojunction tunnel FET\n(TFET) and FinFET devices and 32-bit carry-lookahead adder (CLA) circuit operating in\nnear-threshold region. The impacts of the most severe intrinsic device variations including\nwork function variation (WFV) and fin line-edge roughness (fin LER) on TFET and\nFinFET device Ion, Ioff, Cg, 32-bit CLA delay and power-delay product (PDP) are\ninvestigated and compared using 3D atomistic TCAD mixed-mode Monte-Carlo\nsimulations and HSPICE simulations with look-up table based Verilog-A models\ncalibrated with TCAD simulation results. The results indicate that WFV and fin LER have\ndifferent impacts on device Ion and Ioff. Besides, at low operating voltage (<0.3 V), the CLA\ncircuit delay and power-delay product (PDP) of TFET are significantly better than FinFET\ndue to its better Ion and Cg,ave and their smaller variability. However, the leakage power of\nTFET CLA is larger than FinFET CLA due to the worse Ioff variability of TFET devices....
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