Current Issue : January - March Volume : 2016 Issue Number : 1 Articles : 4 Articles
A novel VLSI architecture for multi-channel online spike sorting is presented in\nthis paper. In the architecture, the spike detection is based on nonlinear energy operator\n(NEO), and the feature extraction is carried out by the generalized Hebbian algorithm\n(GHA). To lower the power consumption and area costs of the circuits, all of the channels\nshare the same core for spike detection and feature extraction operations. Each channel\nhas dedicated buffers for storing the detected spikes and the principal components of that\nchannel. The proposed circuit also contains a clock gating system supplying the clock to\nonly the buffers of channels currently using the computation core to further reduce the power\nconsumption. The architecture has been implemented by an application-specific integrated\ncircuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the\nproposed architecture has lower power consumption and hardware area costs for real-time\nmulti-channel spike detection and feature extraction....
In this paper, we present a solution to the ultra low voltage inverter by adding a keeper transistor\nin order to make the semi-floating-gate more stable and to reduce the current dissipation.\nMoreover, we also present a differential ULV inverter and elaborate on the reliability and fault tolerance\nof the gate. The differential ULV gate compared to both a former ULV gate and standard\nCMOS are given. The results are obtained through Monte-Carlo simulations....
With continued process scaling, CMOS has become a viable technology for the design of high-performance low noise amplifiers\n(LNAs) in the radio frequency (RF) regime. This paper describes the design of RF LNAs using a geometric programming (GP)\noptimization method. An important challenge for RF LNAs designed at nanometer scale geometries is the excess thermal noise\nobserved in the MOSFETs. An extensive survey of analytical models and experimental results reported in the literature is carried\nout to quantify the issue of excessive thermal noise for short-channel MOSFETs. Short channel effects such as channel-length\nmodulation and velocity saturation effects are also accounted for in our optimization process. The GP approach is able to efficiently\ncalculate the globally optimum solution. The approximations required to setup the equations and constraints to allow convex\noptimization are detailed.The method is applied to the design of inductive source degenerated common source amplifiers at the\n90nm and 180nm technology nodes. The optimization results are validated through comparison with numerical simulations using\nAgilent�s Advanced Design Systems (ADS) software....
The gate level body biasing (GLBB) is assessed in the context of ultra-low-voltage logic designs. To this purpose, a GLBB\nmirror full adder is implemented by using a commercial 45nm bulk CMOS triple-well technology and compared to equivalent\nconventional zero body-biased CMOS and dynamic threshold voltage MOSFET (DTMOS) circuits under different running\nconditions. Post layout simulations demonstrate that, at the parity of leakage power consumption, the GLBB technique exhibits a\nsignificant concurrent reduction of the energy per operation and the delay in comparison to the conventional CMOS and DTMOS\napproaches. The silicon area required by the GLBB full adder is halved with respect to the equivalent DTMOS implementation, but\nit is higher in comparison to conventional CMOS design. Performed analysis also proves that the GLBB solution exhibits a high\nlevel of robustness against temperature fluctuations and process variations....
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