Current Issue : April - June Volume : 2016 Issue Number : 2 Articles : 4 Articles
The next-generation video coding standard of High-Efficiency Video Coding (HEVC) is especially efficient for coding\nhigh-resolution video such as 8K-ultra-high-definition (UHD) video. Fractional motion estimation in HEVC presents a\nsignificant challenge in clock latency and area cost as it consumes more than 40 % of the total encoding time and\nthus results in high computational complexity. With aims at supporting 8K-UHD video applications, an efficient\ninterpolation filter VLSI architecture for HEVC is proposed in this paper. Firstly, a new interpolation filter algorithm\nbased on the 8-pixel interpolation unit is proposed in this paper. It can save 19.7 % processing time on average\nwith acceptable coding quality degradation. Based on the proposed algorithm, an efficient interpolation filter\nVLSI architecture, composed of a reused data path of interpolation, an efficient memory organization, and a\nreconfigurable pipeline interpolation filter engine, is presented to reduce the implement hardware area and achieve\nhigh throughput. The final VLSI implementation only requires 37.2k gates in a standard 90-nm CMOS technology at an\noperating frequency of 240 MHz. The proposed architecture can be reused for either half-pixel interpolation or\nquarter-pixel interpolation, which can reduce the area cost for about 131,040 bits RAM. The processing latency of our\nproposed VLSI architecture can support the real-time processing of 4:2:0 format 7680 Ã?â?? 4320@78fps video sequences....
In this paper, a co-design method and a wafer-level packaging technique of a flexible\nantenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are\nproposed. The proposed co-design method optimizes the system architecture, and can help avoid the\nuse of external matching components, resulting in the realization of a small-size system. In addition,\nthe technique employed to assemble a silicon large-scale integration (LSI) chip on the very thin\nparylene film (5 �¼m) enables the integration of the rectifier circuits and the flexible antenna (rectenna).\nIn the demonstration of wireless power transmission (WPT), the fabricated flexible rectenna achieved\na maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with\nradio waves allows a misalignment of 185% against antenna size, implying that the misalignment has\na less effect on the WPT characteristics compared with electromagnetic induction....
The reliability of Very Large Scale Integration (VLSI) circuits has become increasingly\nsusceptible to transient faults induced by environmental noise with the scaling of technology. Some\ncommonly used fault tolerance strategies require statistical methods to accurately estimate the fault\nrate in different parts of the logic circuit, and Monte Carlo (MC) simulation is often applied to\ncomplete this task. However, the MC method suffers from impractical computation costs due to the\nsize of the circuits. Furthermore, circuit aging effects, such as negative bias temperature instability\n(NBTI), will change the characteristics of the circuit during its lifetime, leading to a change in the\ncircuit�s noise margin. This change will increase the complexity of transient fault rate estimation\ntasks. In this paper, an NBTI-aware statistical analysis method based on probability voltage transfer\ncharacteristics is proposed for combinational logic circuit. This method can acquire accurate fault rates\nusing a discrete probability density function approximation process, thus resolving the computation\ncost problem of the MC method. The proposed method can also consider aging effects and analyze\nstatistical changes in the fault rates. Experimental results demonstrate that, compared to the MC\nsimulation, our method can achieve computation times that are two orders of magnitude shorter\nwhile maintaining an error rate less than 9%....
Neuromorphic chips embody computational principles operating in the nervous system, into microelectronic devices. In this domain it is important to identify computational primitives that theory and experiments suggest as generic and reusable cognitive elements. One such element is provided by attractor dynamics in recurrent networks. Point attractors are equilibrium states of the dynamics (up to fluctuations), determined by the synaptic structure of the network; a basin' of attraction comprises all initial states leading to a given attractor upon relaxation, hence making attractor dynamics suitable to implement robust associative memory. The initial network state is dictated by the stimulus, and relaxation to the attractor state implements the retrieval of the corresponding memorized prototypical pattern. In a previous work we demonstrated that a neuromorphic recurrent network of spiking neurons and suitably chosen, fixed synapses supports attractor dynamics. Here we focus on learning: activating on-chip synaptic plasticity and using a theory-driven strategy for choosing network parameters, we show that autonomous learning, following repeated presentation of simple visual stimuli, shapes a synaptic connectivity supporting stimulus-selective attractors. Associative memory develops on chip as the result of the coupled stimulus-driven neural activity and ensuing synaptic dynamics, with no artificial separation between learning and retrieval phases....
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