Current Issue : July - September Volume : 2016 Issue Number : 3 Articles : 4 Articles
An ultra-low leakage current Application Specific Integrated Circuit (ASIC) called\nUtopia (Ultralow Picoammeter) has been designed and fabricated in AMS 0.35 �¼m CMOS, in order\nto be used as the front-end for ionising radiation monitoring at CERN. It is based on the topology\nof a Current to Frequency Converter (CFC) through charge balancing and demonstrates a wide\ndynamic range of 8.5 decades without range changing. Due to a design aimed at minimising input\nleakage currents, input currents as low as 10 fA can be measured....
UM-BUS is a novel dynamically reconfigurable high-speed serial bus for embedded systems. It can achieve fault tolerance by\ndetecting the channel status in real time and reconfigure dynamically at run-time.The bus supports direct interconnections between\nup to eight master nodes and multiple slave nodes. In order to solve the time synchronization problem among master nodes, this\npaper proposes a novel time synchronization method, which can meet the requirement of time precision in UM-BUS. In this\nproposed method, time is firstly broadcasted through time broadcast packets. Then, the transmission delay and time deviations via\nthree handshakes during link self-checking and channel detection can be worked out referring to the IEEE 1588 protocol. Thereby,\neach node calibrates its own time according to the broadcasted time.The proposed method has been proved to meet the requirement\nof real-time time synchronization.The experimental results show that the synchronous precision can achieve a bias less than 20 ns....
A review on CMOS delay lines with a focus on the most frequently used techniques\nfor high-resolution delay step is presented. The primary types, specifications, delay\ncircuits, and operating principles are presented. The delay circuits reported in this\npaper are used for delaying digital inputs and clock signals. The most common analog\nand digitally-controlled delay elements topologies are presented, focusing on the main\ndelay-tuning strategies. IC variables, namely, process, supply voltage, temperature,\nand noise sources that affect delay resolution through timing jitter are discussed. The\ndesign specifications of these delay elements are also discussed and compared for the\ncommon delay line circuits. As a result, the main findings of this paper are highlighting\nand discussing the followings: the most efficient high-resolution delay line techniques,\nthe trade-off challenge found between CMOS delay lines designed using either analog\nor digitally-controlled delay elements, the trade-off challenge between delay resolution\nand delay range and the proposed solutions for this challenge, and how CMOS\ntechnology scaling can affect the performance of CMOS delay lines. Moreover, the current\ntrends and efforts used in order to generate output delayed signal with low jitter\nin the sub-picosecond range are presented....
Embedded systems used in real-time applications require low power, less area and high computation\nspeed. For digital signal processing, image processing and communication applications, data\nare often received at a continuously high rate. The type of necessary arithmetic functions and matrix\noperations may vary greatly among different applications. The RTL-based design and verification\nof one or more of these functions could be time-consuming. Some High Level Synthesis tools\nreduce this design and verification time but may not be optimal or suitable for low power applications.\nThe design tool proposed in this paper can improve the design time and reduce the verification\nprocess. The design tool offers a fast design and verification platform for important matrix\noperations. These operations range from simple addition to more complex matrix operations such\nas LU and QR factorizations. The proposed platform can improve design time by reducing verification\ncycle. This tool generates Verilog code and its testbench that can be realized in FPGA and VLSI\nsystems. The designed system uses MATLAB-based verification and reporting....
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