Current Issue : July - September Volume : 2017 Issue Number : 3 Articles : 6 Articles
Hardware redundancy at different levels of design is a common fault mitigation technique, which is well known for its efficiency to\nthe detriment of area overhead. In order to reduce this drawback, several fault-tolerant techniques have been proposed in literature\nto find a good trade-off. In this paper, critical constituent gates in math circuits are detected and graded based on the impact of\nan error in the output of a circuit.These critical gates should be hardened first under the area constraint of design criteria. Indeed,\noutput bits considered crucial to a system receive higher priorities to be protected, reducing the occurrence of critical errors.The\n74283 fast adder is used as an example to illustrate the feasibility and efficiency of the proposed approach....
We propose a new design, Physical Unclonable Function (PUF) scheme, for the Internet of Things (IoT), which has been suffering\nfrom multiple-level security threats. As more and more objects interconnect on IoT networks, the identity of each thing is very\nimportant. To authenticate each object, we design an impedance mismatch PUF, which exploits random physical factors of the\ntransmission line to generate a security unique private key. The characteristic impedance of the transmission line and signal\ntransmission theory of the printed circuit board (PCB) are also analyzed in detail. To improve the reliability, current feedback\namplifier (CFA) method is applied on the PUF. Finally, the proposed scheme is implemented and tested. The measure results show\nthat impedance mismatch PUF provides better unpredictability and randomness....
This paper presents an implementation of comparator (1-bit)\ncircuit using a MUX-6T based adder cell. MUX-6T full adder cell is\ndesigned with a combination of multiplexing control input and Boolean\nidentities. The proposed comparator design features higher computing\nspeed and lower energy consumption due to the efficient MUX-6T adder\ncell. The design adopts multiplexing technique with control input to\nalleviate the threshold voltage loss problem which is commonly\nencountered in Pass Transistor Logic (PTL) design. The proposed design\nsuccessfully embeds the buffering circuit in the full adder design which\nhelps the cell to operate at lower supply voltage compared with the other\nrelated existing designs. It also enhances the speed of the cascaded\noperation significantly while maintaining the performance edge in energy\nconsumption. In the proposed design, the transistor count is minimized. For\nperformance comparison, the proposed MUX-6T comparator (1-bit) is\ncompared with four existing full adders based comparators using BSIM4\nmodel parameters. The simulations are performed for 65nm process models\nindicate that the proposed design has lowest energy consumption along\nwith the performance edge in both speed and energy consumption. The\nvariants namely area and power of the proposed comparator is also\ncompared with the published author designs to validate its suitability for\nlow power and high speed mobile communication applications....
A true random number generator based on perpendicularly magnetized voltagecontrolled\nmagnetic tunnel junction devices (MRNG) is presented. Unlike MTJs used\nin memory applications where a stable bit is needed to store information, in this\nwork, the MTJ is intentionally designed with small perpendicular magnetic anisotropy\n(PMA). This allows one to take advantage of the thermally activated fluctuations\nof its free layer as a stochastic noise source. Furthermore, we take advantage of\nthe voltage dependence of anisotropy to temporarily change the MTJ state into an\nunstable state when a voltage is applied. Since the MTJ has two energetically stable\nstates, the final state is randomly chosen by thermal fluctuation. The voltage controlled\nmagnetic anisotropy (VCMA) effect is used to generate the metastable state\nof the MTJ by lowering its energy barrier. The proposed MRNG achieves a high\nthroughput (32 Gbps) by implementing a 64 Ã?â?? 64 MTJ array into CMOS circuits and\nexecuting operations in a parallel manner. Furthermore, the circuit consumes very low\nenergy to generate a random bit (31.5 fJ/bit) due to the high energy efficiency of the\nvoltage-controlled MTJ switching....
This paper presents an improved VLSI (Very Large Scale of Integration) architecture for\nreal-time and high-accuracy computation of trigonometric functions with fixed-point arithmetic,\nparticularly arctangent using CORDIC (Coordinate Rotation Digital Computer) and fast magnitude\nestimation. The standard CORDIC implementation suffers of a loss of accuracy when the magnitude\nof the input vector becomes small. Using a fast magnitude estimator before running the standard\nalgorithm, a pre-processing magnification is implemented, shifting the input coordinates by a proper\nfactor. The entire architecture does not use a multiplier, it uses only shift and add primitives\nas the original CORDIC, and it does not change the data path precision of the CORDIC core.\nA bit-true case study is presented showing a reduction of the maximum phase error from 414 LSB\n(angle error of 0.6355 rad) to 4 LSB (angle error of 0.0061 rad), with small overheads of complexity\nand speed. Implementation of the new architecture in 0.18 �¼m CMOS technology allows for\nreal-time and low-power processing of CORDIC and arctangent, which are key functions in many\nembedded DSP systems. The proposed macrocell has been verified by integration in a system-on-chip,\ncalled SENSASIP (Sensor Application Specific Instruction-set Processor), for position sensor signal\nprocessing in automotive measurement applications....
Energy-harvesting passive RFID (radio frequency identification) tags provide countless\npossibilities as so-called smart tags. Smart tags can communicate with existing RFID readers or\ninterrogators while providing a battery-less platform for internal and external sensors to enrich\navailable information about the environment and smart tag it. A reduced cost and size as well as\nan increased lifespan and durability of battery-free smart tags offer improvements in areas such as\ntransportation and product tracking. Battery-free smart tags can ideally support arbitrarily complex\nsensor measurements, but in reality energy limitations can introduce great reductions in operating\nrange and thus application range. In this work, we present an example application of a smart tag with\na passive HF (high-frequency) RFID tag IC (integrated circuit) and MEMS (micro electro-mechanical\nstructure) sensor. A standard HF RFID reader connected to a PC (personal computer) allowed the RF\n(radio frequency) field to power and communicate with the smart tag. A Kalman filter, implemented\non a PC, was used to correct and improve the raw sensor data of smart tag orientation. Measurement\nresults showed that the MEMS sensor on the smart tag could be powered for continuous operation\nand that raw smart tag orientation data could be read while in the RF field of a standard HF RFID\nreader, but at a limited range....
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