Current Issue : January - March Volume : 2012 Issue Number : 1 Articles : 6 Articles
A low-power and low-jitter 12-bit CMOS digitally controlled oscillator (DCO) design is presented. The Low-Power CMOS DCO is designed based on the ring oscillator implemented with Schmitt trigger inverters. The proposed DCO circuit uses control codes of thermometer type to reduce jitters. Performance of the DCO is verified through a novel All Digital Phase-Locked Loop (ADPLL) designed with a unique lock-in process by employing a time-to-digital converter, where both the frequency of the reference clock and the delay between DCO_output and DCO_clock is measured. A carefully designed reset process reduces the phase acquisition process to two cycles. The ADPLL was implemented using the 32?nm Predictive Technology Model (PTM) at 0.9?V supply voltage, and the simulation results show that the proposed ADPLL achieves 10 and 2 reference cycles of frequency and phase acquisitions, respectively, at 700?MHz with less than 67?ps peak-to-peak jitter. The DCO consumes 2.2?mW at 650?MHz with 0.9?V power supply....
An instrumentation channel is designed, implemented, and tested in a 0.5-�µm SiGe BiCMOS process. The circuit features a reconfigurable Wheatstone bridge network that interfaces an assortment of external sensors to signal processing circuits. Also, analog sampling is implemented in the channel using a flying capacitor configuration. The analog samples are digitized by a lowpower multichannel A/D converter. Measurement results show that the instrumentation channel supports input signals up to 200 Hz and operates across a wide temperature range of -180?C to 125?C. This work demonstrates the use of a commercially available first generation SiGe BiCMOS process in designing circuits suitable for extreme environment applications....
Two novel theorems are developed which prove that certain logic functions are more robust to errors than others. These theorems are used to construct datapath circuits that give an increased immunity to error over other naive implementations. A link between probabilistic operation and ultra-low energy computing has been shown in prior work. These novel theorems and designs will be used to further improve probabilistic design of ultra-low power datapaths. This culminates in an asynchronous design for the maximum amount of energy savings per a given error rate. Spice simulation results using a commercially available and well-tested 0.25 �µm technology are given verifying the ultra-low power, probabilistic full-adder designs. Further, close to 6X energy savings is achieved for a probabilistic full-adder over the deterministic case....
The Scalable Parallel Random Number Generators (SPRNGs) library is widely used in computational science applications such\nas Monte Carlo simulations since SPRNG supports fast, parallel, and scalable random number generation with good statistical\nproperties. In order to accelerate SPRNG, we develop a Hardware-Accelerated version of SPRNG (HASPRNG) on the Xilinx\nXC2VP50 Field Programmable Gate Arrays (FPGAs) in the Cray XD1 that produces identical results. HASPRNG includes the\nreconfigurable logic for FPGAs along with a programming interface which performs integer random number generation. To\ndemonstrate HASPRNG for Reconfigurable Computing (RC) applications, we also develop a Monte Carlo p-estimator for the\nCray XD1. The RC Monte Carlo p-estimator shows a 19.1Ã?â?? speedup over the 2.2 GHz AMD Opteron processor in the Cray XD1.\nIn this paper we describe the FPGA implementation for HASPRNG and a p-estimator example application exploiting the finegrained\nparallelism and mathematical properties of the SPRNG algorithm....
A novel Capacitor array structure for Successive Approximation Register (SAR) ADC is proposed. This circuit efficiently utilizes charge recycling to achieve high-speed of operation and it can be applied to high-speed and low-to-medium-resolution SAR ADC. The parasitic effects and the static linearity performance, namely, the INL and DNL, of the proposed structure are theoretically analyzed and behavioral simulations are performed to demonstrate its effectiveness under those nonidealities. Simulation results show that to achieve the same conversion performance the proposed capacitor array structure can reduce the average power consumed from the reference ladder by 90% when compared to the binary-weighted splitting capacitor array structure....
A post-clock-tree-synthesis (post-CTS) optimization method is proposed that suggests delay insertion at the leaves of the clock tree in order to implement a limited version of clock skew scheduling. Delay insertion is limited on each clock tree branch simultaneous with a global monitoring of the total amount of delay insertion. The delay insertion for nonzero clock skew operation is performed only at the clock sinks in order to preserve the structure and the optimizations implemented in the clock tree synthesis stage. The methodology is implemented as a linear programming model amenable to two design objectives: fixing timing violations or optimizing the clock period. Experimental results show that the clock networks of the largest ISCAS'89 circuits can be corrected post-CTS to resolve the timing conflicts in approximately 90% of the circuits with minimal delay insertion (0.159??Ã?â????clock period per clock path on average). It is also shown that the majority of the clock period improvement achievable through unrestricted clock skew scheduling are obtained through very limited insertion (Ã?Å? 43% average improvement through 10% of max insertion)....
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