Current Issue : January - March Volume : 2019 Issue Number : 1 Articles : 5 Articles
A two-parameter autonomous jerk oscillator with a cosine hyperbolic nonlinearity is proposed in this paper. Firstly, the stability of\nequilibrium points of proposed autonomous jerk oscillator is investigated by analyzing the characteristic equation and the existence\nof Hopf bifurcation is verified using one of the two parameters as a bifurcation parameter. By tuning its two parameters, various\ndynamical behaviors are found in the proposed autonomous jerk oscillator including periodic attractor, one-scroll chaotic attractor,\nand coexistence between chaotic and periodic attractors.The proposed autonomous jerk oscillator has period-doubling route to\nchaos with the variation of one of its parameters and reverse period-doubling route to chaos with the variation of its other parameter.\nThe proposed autonomous jerk oscillator is modelled on Field Programmable Gate Array (FPGA) and the FPGA chip statistics\nand phase portraits are derived. The chaotic and coexistence of attractors generated in the proposed autonomous jerk oscillator\nare confirmed by FPGA implementation of the proposed autonomous jerk oscillator. A good qualitative agreement is illustrated\nbetween the numerical and FPGA results. Finally synchronization of unidirectional coupled identical proposed autonomous jerk\noscillators is achieved using adaptive sliding mode control method....
Ternary content-addressable memories (TCAMs) are used to design high-speed search\nengines. TCAM is implemented on application-specific integrated circuit (native TCAMs) and\nfield-programmable gate array (FPGA) (static random-access memory (SRAM)-based TCAMs)\nplatforms but both have the drawback of high power consumption. This paper presents a\npre-classifier-based architecture for an energy-efficient SRAM-based TCAM. The first classification\nstage divides the TCAM table into several sub-tables of balanced size. The second SRAM-based\nimplementation stage maps each of the resultant TCAM sub-tables to a separate row of configured\nSRAM blocks in the architecture. The proposed architecture selectively activates at most one row\nof SRAM blocks for each incoming TCAM word. Compared with the existing SRAM-based TCAM\ndesigns on FPGAs, the proposed design consumes significantly reduced energy as it activates a part\nof SRAM memory used for lookup rather than the entire SRAM memory as in the previous schemes.\nWe implemented the proposed approach sample designs of size 512 Ã? 36 on Xilinx Virtex-6 FPGA.\nThe experimental results showed that the proposed design achieved at least three times lower power\nconsumption per performance than other SRAM-based TCAM architectures....
Wireless Sensor Networks (WSN) aim at linking the cyber and physical worlds. Their security has taken relevance due to the\nsensitive data these networks might process under unprotected physical and cybernetic environments.The operational constraints\nin the sensor nodes demand security primitives with small implementation size and low power consumption. Authenticated\nencryption is a mechanism to provide these systems with confidentiality, integrity, and authentication of sensitive data. In this\npaper we explore hardware implementation alternatives of authenticated encryption through generic compositions, to assess the\ncosts of this security approach in WSN. Two symmetric ciphers, AES and Present, and two hash functions, SHA and spongent,\nare used as the underlying primitives for the generic compositions. All the architectures studied in this work are implemented and\nevaluated in an FPGA-based WSN mote.The life time of the sensor node is used as the main evaluation metric but FPGA resources\nare also reported. From the experimental results obtained, it is shown how lightweight ciphers significantly contribute to reduce\nimplementation area and energy consumption overheads, extending the lifetime of the sensor node....
As the performance of digital devices is improving, Hardware-In-the-Loop (HIL) techniques\nare being increasingly used. HIL systems are frequently implemented using FPGAs (Field Programmable\nGate Array) as they allow faster calculations and therefore smaller simulation steps. As the simulation\nstep is reduced, the incremental values for the state variables are reduced proportionally, increasing the\ndifference between the current value of the state variable and its increments. This difference can lead to\nnumerical resolution issues when both magnitudes cannot be stored simultaneously in the state variable.\nFPGA-based HIL systems generally use 32-bit floating-point due to hardware and timing restrictions but\nthey may suffer from these resolution problems. This paper explores the limits of 32-bit floating-point\narithmetics in the context of hardware-in-the-loop systems, and how a larger format can be used to avoid\nresolution problems. The consequences in terms of hardware resources and running frequency are also\nexplored. Although the conclusions reached in this work can be applied to any digital device, they can be\ndirectly used in the field of FPGAs, where the designer can easily use custom floating-point arithmetics...
Physical Unclonable Functions (PUFs) are hardware security primitives that are increasingly\nbeing used for authentication and key generation in ICs and FPGAs. For space systems, they are a\npromising approach to meet the needs for secure communications at low cost. To this purpose, it is\nessential to determine if they are reliable in the space radiation environment. In this work we evaluate\nthe Total Ionizing Dose effects on a delay-based PUF implemented in SRAM-FPGA, namely a Ring\nOscillator PUF. Several major quality metrics have been used to analyze the evolution of the PUF\nresponse with the total ionizing dose. Experimental results demonstrate that total ionizing dose has a\nperceptible effect on the quality of the PUF response, but it could still be used for space applications\nby making some appropriate corrections...
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