Current Issue : April - June Volume : 2019 Issue Number : 2 Articles : 5 Articles
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Clustering is the most common method for organizing unlabeled data into its natural\ngroups (called clusters), based on similarity (in some sense or another) among data objects. The\nPartitioning Around Medoids (PAM) algorithm belongs to the partitioning-based methods of\nclustering widely used for objects categorization, image analysis, bioinformatics and data\ncompression, but due to its high time complexity, the PAM algorithm cannot be used with large\ndatasets or in any embedded or real-time application. In this work, we propose a simple and scalable\nparallel architecture for the PAM algorithm to reduce its running time. This architecture can easily\nbe implemented either on a multi-core processor system to deal with big data or on a reconfigurable\nhardware platform, such as FPGA and MPSoCs, which makes it suitable for real-time clustering\napplications. Our proposed model partitions data equally among multiple processing cores. Each\ncore executes the same sequence of tasks simultaneously on its respective data subset and shares\nintermediate results with other cores to produce results. Experiments show that the computational\ncomplexity of the PAM algorithm is reduced exponentially as we increase the number of cores\nworking in parallel. It is also observed that the speedup graph of our proposed model becomes more\nlinear with the increase in number of data points and as the clusters become more uniform. The\nresults also demonstrate that the proposed architecture produces the same results as the actual PAM\nalgorithm, but with reduced computational complexity....
Because of its high resolution, low cost, small volume, low power dissipation and less\nconversion time consumption, the direct digital synthesizer (DDS) method has been applied more and\nmore in the fields of frequency synthesis and signal generation. However, only a limited number of\nprecise frequency signals can be synthesized by the traditional DDS, for the reason that its accumulator\nmodulus is fixed, and its frequency tuning word must be integer. In this paper, a precise DDS method\nusing compound frequency tuning word is proposed, which improves the accuracy of synthesized\nsignals at any frequency points on the premise of guaranteeing the stability of synthesized signals.\nIn order to verify the effectiveness of the new method, a DDS frequency synthesizer based on FPGA\nis designed and implemented. Taking the rubidium atomic clock PRS10 as standard frequency\nsource, the experiments shows that the frequency stability of the synthesized signal is better than\n8.0 * 10-12/s, the relative frequency error is less than 4.8 * 10-12, and that the frequency accuracy is\nimproved by three orders of magnitude compared with the traditional DDS method....
Due to the complicated circuit topology and high switching frequency, field-programmable\ngate arrays (FPGA) can stand up to the challenges for the hardware in the loop (HIL) real-time\nsimulation of power electronics converters. The Associated Discrete Circuit (ADC) modeling method,\nwhich has a fixed admittance matrix, greatly reduces the computation cost for FPGA. However,\nthe oscillations introduced by the switch-equivalent model reduces the simulation accuracy. In this\npaper, firstly, a novel algorithm is proposed to determine the optimal discrete-time switch admittance\nparameter, Gs, which is obtained by minimizing the switching loss. Secondly, the FPGA resource\noptimization method, in which the simulation time step, bit-length, and model precision are taken\ninto consideration, is presented when the power electronics converter is implemented in FPGA.\nFinally, the above method is validated on the topology of a three-phase inverter with LC filters.\nThe HIL simulation and practicality experiments verify the effect of FPGA resource optimization and\nthe validity of the ADC modeling method, respectively....
To improve the road feeling of the steer-by-wire (SBW)system, a fractional order PID(proportion-integral-derivative) methodwith\na fault tolerant module is proposed in this paper. Firstly, the overall road feeling control strategy of the SBWsystem is introduced,\nand then the mathematical model of road feeling control is established. Secondly, a fractional order PID (FOPID) controller is\ndesigned to control torque of the road feeling motor. Furthermore, genetic algorithm (GA) is applied to tune the FOPIDcontrollerâ??s\nparameters. Thirdly, a fault tolerant module aiming at potential failures of the motorâ??s torque sensor is studied to improve the\nreliability of the system. Kalman Filter (KF) algorithm is utilized in the fault tolerant module so as to detect failures of the motorâ??s\ntorque sensor, and then fault tolerant module reconfigures the motorâ??s torque estimated by KF as a substitute when the torque\nsensor fails. Finally, simulations based onMATLAB are performed with the proposed control strategy to identify its performance,\nand the results demonstrate that the proposed control method is feasible and accurate....
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