Current Issue : January - March Volume : 2020 Issue Number : 1 Articles : 5 Articles
The use of Hardware-in-the-Loop (HIL) systems implemented in Field Programmable\nGate Arrays (FPGAs) is constantly increasing because of its advantages compared to traditional\nsimulation techniques. This increase in usage has caused new challenges related to the improvement\nof their performance and features like the number of output channels, while the price of HIL systems\nis diminishing. At present, the use of low-speed Digital-to-Analog Converters (DACs) is starting to\nbe a commercial possibility because of two reasons. One is their lower price and the other is their\nlower pin count, which determines the number and price of the FPGAs that are necessary to handle\nthose DACs. This paper compares four filtering approaches for providing suitable data to low-speed\nDACs, which help to filter high-speed input signals, discarding the need of using expensive highspeed\nDACS, and therefore decreasing the total cost of HIL implementations. Results show that the\nselection of the appropriate filter should be based on the type of the input waveform and the relative\nimportance of the dynamics versus the area....
With the widespread application of WIFI networks and embedded system\ntechnology, the device monitoring system based on Embedded System and\nwireless network came into being. In this paper, we introduce a device monitoring\nsystem based on ARM upper computer and WIFI transmission, and\nwe tested this system on workshop equipment. The hardware adopts ARM\nCortex-A8 processor architecture of TI company as the main control chip,\nusing IAC-335X-Kit development board for system design, external USB\ncamera module and WIFI wireless module for video capture and data transmission.\nThe software is based on embedded Linux as the platform. The system\nwill collect production data accurately and objectively, and the statistical\nanalysis. At the same time, the system uses QT to develop the upper computer\nsoftware GUI interface. Compared with the traditional system based on the\nwired network, our design is more convenient and flexible, which reduces the\nimplementation restriction and maintenance cost of traditional network\ncabling....
The development of modern networking requires that high-performance network\nprocessors be designed quickly and efficiently to support new protocols. As a very important\npart of the processor, the parser parses the headers of the packetsâ??this is the precondition for\nfurther processing and finally forwarding these packets. This paper presents a framework designed\nto transform P4 programs to VHDL and to generate parsers on Field Programmable Gate Arrays\n(FPGAs). The framework includes a pipeline-based hardware architecture and a back-end compiler.\nThe hardware architecture comprises many components with varying functionality, each of which\nhas its own optimized VHDL template. By using the output of a standard frontend P4 compiler,\nour proposed compiler extracts the parameters and relationships from within the used components,\nwhich can then be mapped to corresponding templates by configuring, optimizing, and instantiating\nthem. Finally, these templates are connected to output VHDL code. When a prototype of this\nframework is implemented and evaluated, the results demonstrate that the throughputs of the\ngenerated parsers achieve nearly 320 Gbps at a clock rate of around 300 MHz. Compared with\nstate-of-the-art solutions, our proposed parsers achieve an average of twice the throughput when\nsimilar amounts of resources are being used....
Dimensionality reduction is an important research area for hyperspectral remote sensing\nimages due to the redundancy of spectral information. Sparsity preserving projection (SPP) is a\ndimensionality reduction (DR) algorithm based on the l1-graph, which establishes the relations of\nsamples by sparse representation. However, SPP is an unsupervised algorithm that ignores the label\ninformation of samples and the objective function of SPP; instead, it only considers the reconstruction\nerror, which means that the classification effect is constrained. In order to solve this problem,\nthis paper proposes a dimensionality reduction algorithm called the supervised sparse embedded\npreserving projection (SSEPP) algorithm. SSEPP considers the manifold structure information of\nsamples and makes full use of the label information available in order to enhance the discriminative\nability of the projection subspace. While maintaining the sparse reconstruction error, the algorithm\nalso minimizes the error between samples of the same class. Experiments were performed on an\nIndian Pines hyperspectral dataset and HJ1A-HSI remote sensing images from the Zhangjiang estuary\nin Southeastern China, respectively. The results show that the proposed method effectively improves\nits classification accuracy....
A third of the food produced in the world ends up in the rubbish, enough to put an\nend to world hunger. On the other hand, society is increasingly concerned to bring healthy eating\nhabits. A RFID (radio frequency identification) food management system is designed to palliate the\npreviously described issues in an Internet of Things (IoT) network paradigm. It consists of RFID\nreaders placed on a userâ??s kitchen furniture, which automatically reads food information. There is\nno need for direct sight between reader and tag, as it occurs through the barcode technology. As a\ncomplement, a multi-platform web application is developed, allowing its users to check the date of\nfood expiration and other detailed information. The application notifies the user when a product is\nabout to expire. It also offers recipes that might be prepared with available foods, thus preventing\nthem from being wasted. The recipes are accompanied by their nutritional information, so that the\nuser can exhaustively monitor what he/she eats. This embedded system may provide economic\nbenefits to the manufacturer, since it allows supermarkets to pay for displaying their products\nadvertised through the application. After system deployment, design conclusions are shown, and\nfuture improvement points are indicated....
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