Current Issue : April - June Volume : 2020 Issue Number : 2 Articles : 5 Articles
In this paper, a novel coupler/reflection-type programmable electronic impedance tuner\ncombined with switches that were fabricated by a 0.18-um complementary metalâ??oxideâ??\nsemiconductor (CMOS) silicon-on-insulator (SOI) process is proposed for replacement of the\nconventional mechanical tuner in power amplifier (PA) load-pull test. By employing the multistacked\nfield-effect transistors (FETs) as a single-branch switch, the proposed tuner has the\nadvantage of precise impedance variation with systematic and magnitude and phase adjustment.\nAdditionally, it led to high standing wave ratio (SWR) coverage and a good impedance resolution\nwith a high power handling capability. Furthermore, the double-branch based on multi-stacked FET\nwas applied to switches for additional enhancement of the intermodulation distortion (IMD)\nperformance through the mitigated drain-source voltage of the single-FET. .....................................
The performances of two RF transmitters, monolithically integrated with their antennas\non a single CMOS microchip fabricated in a standard 0.35 microm process, are presented. The usage\nof these architectures in the Internet of Things (IoT) paradigm is envisioned, as part of a custom\nconceived data transmission system. The implemented circuits use two different directly onâ??off\nkeying (OOK) modulated oscillator topologies whose outputs are employed to feed two loop antennas.\nThe powering of both transmitters is duty-cycled for reducing the average power consumption to a\nfew tenths of a microwatt, allowing the usage as low-power transmitters for IoT nodes. The integrated\nloop antennas radiate sufficient power for a few metersâ?? communication range. The OOK transmitted\nsignal can be easily detected using a commercial receiver....
The delay bound in system on chips (SoC) represents the worst-case traverse time of on-chip\ncommunication. In network on chip (NoC)-based SoC, optimizing the delay bound is challenging due\nto two aspects: (1) the delay bound is hard to obtain by traditional methods such as simulation; (2) the\ndelay bound changes with the different application mappings. In this paper, we propose a delay\nbound optimization method using discrete firefly optimization algorithms (DBFA). First, we present\na formal analytical delay bound model based on network calculus for both unipath and multipath\nrouting in NoCs. We then set every flow in the application as the target flow and calculate the\ndelay bound using the proposed model. Finally, we adopt firefly algorithm (FA) as the optimization\nmethod for minimizing the delay bound. We used industry patterns (video object plane decoder\n(VOPD), multiwindow display (MWD), etc.) to verify the effectiveness of delay bound optimization\nmethod. Experiments show that the proposed method is both effective and reliable, with a maximum\noptimization of 42.86%....
In this paper, a transimpedance amplifier (TIA) based on floating active inductors (FAI)\nis presented. Compared with conventional TIAs, the proposed TIA has the advantages of a wider\nbandwidth, lower power dissipation, and smaller chip area. The schematics and characteristics of the FAI\ncircuit are explained. Moreover, the proposed TIA employs the combination of capacitive degeneration,\nthe broadband matching network, and the regulated cascode input stage to enhance the bandwidth and\ngain. This turns the TIA design into a fifth-order low pass filter with Butterworth response. The TIA is\nimplemented using 0.18 microm Rohm CMOS technology and consumes only 10.7 mW with a supply voltage\nof 1.8 V. .........................................
The effect on the gas permeance properties and structural morphology of the presence\nof methyl functional groups in a silica membrane was studied. Membranes were synthesized via\nchemical vapor deposition (CVD) at 650 Degree C and atmospheric pressure using three silicon compounds\nwith differing numbers of methyl- and methoxy-functional groups: tetramethyl orthosilicate (TMOS),\nmethyltrimethoxysilane (MTMOS), and dimethyldimethoxysilane (DMDMOS). The residence time\nof the silica precursors in the CVD process was adjusted for each precursor and optimized in\nterms of gas permeance and ideal gas selectivity criteria������....
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