Current Issue : April - June Volume : 2020 Issue Number : 2 Articles : 5 Articles
Diabetic retinopathy (DR) and glaucoma are common eye diseases that affect a blood\nvessel in the retina and are two of the leading causes of vision loss around the world. Glaucoma is a\ncommon eye condition where the optic nerve that connects the eye to the brain becomes damaged,\nwhereas DR is a complication of diabetes caused by high blood sugar levels damaging the back of\nthe eye. In order to produce an accurate and early diagnosis, an extremely high number of retinal\nimages needs to be processed. Given the required computational complexity of image processing\nalgorithms and the need for high-performance architectures, this paper proposes and demonstrates\nthe use of fully parallel field programmable gate arrays (FPGAs) to overcome the burden of real-time\ncomputing in conventional software architectures. The experimental results achieved through software\nimplementation were validated on an FPGA device. The results showed a remarkable improvement\nin terms of computational speed and power consumption. This paper presents various preprocessing\nmethods to analyse fundus images, which can serve as a diagnostic tool for detection of glaucoma and\ndiabetic retinopathy. In the proposed adaptive thresholding-based preprocessing method, features\nwere selected by calculating the area of the segmented optic disk, which was further classified\nusing a feedforward neural network (NN). The analysis was carried out using feature extraction\nthrough existing methodologies such as adaptive thresholding, histogram and wavelet transform.\nResults obtained through these methods were quantified to obtain optimum performance in terms of\nclassification accuracy. The proposed hardware implementation outperforms existing methods and\noffers a significant improvement in terms of computational speed and power consumption....
One of the main techniques for debugging power converters is hardware-in-the-loop (HIL),\nwhich is used for real-time emulation. Field programmable gate arrays (FPGA) are the most common\ndesign platforms due to their acceleration capability. In this case, the widths of the signals have to be\ncarefully chosen to optimize the area and speed. For this purpose, fixed-point arithmetic is one of the\nbest options because although the design time is high, it allows the personalization of the number of\nbits in every signal. The representation of state variables in power converters has been previously\nstudied, however other signals, such as feedback signals, can also have a big influence because they\ntransmit the value of one state variable to the rest, and vice versa. This paper presents an analysis of\nthe number of bits in the feedback signals of a boost converter, but the conclusions can be extended to\nother power converters. The purpose of this work is to study how many bits are necessary in order to\navoid the loss of information, but also without wasting bits. Errors of the state variables are obtained\nwith different sizes of feedback signals. These show that the errors in each state variable have similar\npatterns. When the number of bits increases, the error decreases down to a certain number of bits,\nwhere an almost constant error appears. However, when the bits decrease, the error increases linearly.\nFurthermore, the results show that there is a direct relation between the number of bits in feedback\nsignals and the inputs of the converter in the global error. Finally, a design criterion is given to choose\nthe optimum width for each feedback signal, without wasting bits....
This paper proposes a simple and efficient FPGA-based architecture of the overlapping/\nwindowing and overlap-add methods for real-time FFT/IFFT-based signal processing algorithms.\nThe analyzed signal is divided into short-time overlapping frames that are windowed before applying\nFourier analysis/synthesis. Then, the original signal is reconstructed from the windowed (modified)\nframes using the overlap-add (OLA) technique. The proposed architecture was implemented on Field\nProgrammable Gate Array (FPGA) using a high-level programming tool in MATLAB/SIMULINK\nenvironment. Its performance was evaluated on artificial and actual signals using objective metrics....
Combining a pair of materials of different structural dimensions and functional properties\ninto a hybrid material system may realize unprecedented multi-functional device applications.\nEspecially, two-dimensional (2D) materials are suitable for being incorporated into the heterostructures\ndue to their colossal area-to-volume ratio, excellent flexibility, and high sensitivity to interfacial\nand surface interactions. Semiconducting molybdenum disulfide (MoS2), one of the well-studied\nlayered materials, has a direct band gap as one molecular layer and hence, is expected to be one\nof the promising key materials for next-generation optoelectronics. Here, using lateral 2D/3D\nheterostructures composed of MoS2 monolayers and nanoscale inorganic ferroelectric thin films,\nreversibly tunable photoluminescence has been demonstrated at the microscale to be over 200%\nupon ferroelectric polarization reversal by using nanoscale conductive atomic force microscopy\ntips. Also, significant ferroelectric-assisted modulation in electrical properties has been achieved\nfrom field-effect transistor devices based on the 2D/3D heterostructrues. Moreover, it was also\nshown that the MoS2 monolayer can be an effective electric field barrier in spite of its sub-nanometer\nthickness. These results would be of close relevance to exploring novel applications in the fields of\noptoelectronics and sensor technology....
Radiation effects can induce severe and diverse soft errors in digital circuits and systems. A\nXilinx commercial 16 nm FinFET static random-access memory (SRAM)-based field-programmable\ngate array (FPGA) was selected to evaluate the radiation sensitivity and promote the space application\nof FinFET ultra large-scale integrated circuits (ULSI). Picosecond pulsed laser and high energy heavy\nions were employed for irradiation. Before the tests, SRAM-based configure RAMs (CRAMs) were\ninitialized and configured. The 100% embedded block RAMs (BRAMs) were utilized based on the\nVivado implementation of the compiled hardware description language. No hard error was observed\nin both the laser and heavy-ion test. The thresholds for laser-induced single event upset (SEU) were\napprox.3.5 nJ, and the SEU cross-sections were correlated positively to the laserâ??s energy. Multi-bit upsets\nwere measured in heavy-ion and high-energy laser irradiation. Moreover, latch-up and functional\ninterrupt phenomena were common, especially in the heavy-ion tests. The single event effect results\nfor the 16 nm FinFET process were significant, and some radiation tolerance strategies were required\nin a radiation environment....
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