Current Issue : April - June Volume : 2012 Issue Number : 2 Articles : 6 Articles
Malicious software has become a major threat to computer users on the Internet today. Security researchers need to gather and\r\nanalyze large sample sets to develop effective countermeasures. The setting of honeypots, which emulate vulnerable applications,\r\nis one method to collect attack code. We have proposed a dedicated hardware architecture for honeypots which allows both highspeed\r\noperation at 10 Gb/s and beyond and offers a high resilience against attacks on the honeypot infrastructure itself. In this\r\nwork, we refine the base NetStage architecture for better management and scalability. Using dynamic partial reconfiguration, we\r\ncan now update the functionality of the honeypot during operation. To allow the operation of a larger number of vulnerability\r\nemulation handlers, the initial single-device architecture is extended to scalable multichip systems. We describe the technical\r\naspects of these modifications and show results evaluating an implementation on a current quad-FPGA reconfigurable computing\r\nplatform....
Dynamically reconfigurable computing platforms provide promising methods for dynamic management of hardware resources,\npower, and performance. Yet, progress in dynamically reconfigurable computing is fundamentally limited by the reconfiguration\ntime overhead. Prior research in the development of dynamic partial reconfiguration (DPR) controllers has been limited by its use\nof the Processor Local Bus (PLB). As a result, the bus was unavailable during DPR. This resulted in significant time overhead.\nTo minimize the overhead, we introduce the use of a multiport memory controller (MPMC) that frees the PLB during the\nreconfiguration process. The processor is thus allowed to switch to other tasks during the reconfiguration operation. This effectively\nlimits the reconfiguration overhead. An interrupt is used to inform the processor when the operation is complete. Therefore, the\nsystem can multitask during the reconfiguration operation. Furthermore, to maximize performance, we introduce the use of\noverclocking with active feedback. During overclocking, the use of active feedback is used to ensure that the device voltage and\ntemperature are within nominal operating conditions. All of these contributions lead to significant performance improvements\nover current partial reconfiguration subsystems. The portability of the system, demonstrated on the Virtex-4 and the Virtex-5,\nconsists of four different hardware platforms....
SRAM-based fingerprinting uses deviations in power-up behaviour caused by the CMOS fabrication process to identify distinct\r\ndevices. This method is a promising technique for unique identification of physical devices. In the case of SRAM-based hardware\r\nreconfigurable devices such as FPGAs, the integrated SRAM cells are often initialized automatically at power-up, sweeping potential\r\nidentification data. We demonstrate an approach to utilize unused parts of configuration memory space for device identification.\r\nBased on a total of over 200,000 measurements on nine Xilinx Virtex-5 FPGAs, we show that the retrieved values have promising\r\nproperties with respect to consistency on one device, variety between different devices, and stability considering temperature\r\nvariation and aging....
We present a highly productive approach to hardware design based on a many-core microarchitectural template used to implement\r\ncompute-bound applications expressed in a high-level data-parallel language such as OpenCL. The template is customized on a\r\nper-application basis via a range of high-level parameters such as the interconnect topology or processing element architecture.\r\nThe key benefits of this approach are that it (i) allows programmers to express parallelism through an API defined in a high-level\r\nprogramming language, (ii) supports coarse-grainedmultithreading and fine-grained threading while permitting bit-level resource\r\ncontrol, and (iii) reduces the effort required to repurpose the system for different algorithms or different applications.We compare\r\ntemplate-driven design to both full-custom and programmable approaches by studying implementations of a compute-bound\r\ndata-parallel Bayesian graph inference algorithm across several candidate platforms. Specifically, we examine a range of templatebased\r\nimplementations on both FPGA and ASIC platforms and compare each against full custom designs. Throughout this study,\r\nwe use a general-purpose graphics processing unit (GPGPU) implementation as a performance and area baseline. We show that\r\nour approach, similar in productivity to programmable approaches such as GPGPU applications, yields implementations with\r\nperformance approaching that of full-custom designs on both FPGA and ASIC platforms....
Tracking individuals is a prominent application in such domains like surveillance or smart environments. This paper provides\r\na development of a multiple camera setup with jointed view that observes moving persons in a site. It focuses on a geometrybased\r\napproach to establish correspondence among different views. The expensive computational parts of the tracker are hardware\r\naccelerated via a novel system-on-chip (SoC) design. In conjunction with this vision application, a hardware object request broker\r\n(ORB) middleware is presented as the underlying communication system. The hardware ORB provides a hardware/software\r\narchitecture to achieve real-time intercommunication among multiple smart cameras. Via a probing mechanism, a performance\r\nanalysis is performed to measure network latencies, that is, time traversing the TCP/IP stack, in both software and hardware ORB\r\napproaches on the same smart camera platform. The empirical results show that using the proposed hardware ORB as client and\r\nserver in separate smart camera nodes will considerably reduce the network latency up to 100 times compared to the software\r\nORB....
Partial reconfiguration (PR) is an FPGA feature that allows the modification of certain parts of an FPGA while the rest of the\r\nsystem continues to operate without disruption. This distinctive characteristic of FPGAs has many potential benefits but also\r\nchallenges. The lack of good CAD tools and the deep hardware knowledge requirement result in a hard-to-use feature. In this\r\npaper, the new partition-based Xilinx PR flow is used to incorporate PR within our MPI-based message-passing framework to\r\nallow hardware designers to create template bitstreams, which are predesigned, prerouted, generic bitstreams that can be reused\r\nfor multiple applications. As an example of the generality of this approach, four different applications that use the same template\r\nbitstream are run consecutively, with a PR operation performed at the beginning of each application to instantiate the desired\r\napplication engine. We demonstrate a simplified, reusable, high-level, and portable PR interface for X86-FPGA hybrid machines.\r\nPR issues such as local resets of reconfigurable modules and context saving and restoring are addressed in this paper followed by\r\nsome examples and preliminary PR overhead measurements....
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