Current Issue : July - September Volume : 2012 Issue Number : 3 Articles : 6 Articles
Multiple-antenna systems are a promising approach to increase the data rate of wireless communication systems. One efficient\r\npossibility is spatialmultiplexing of the transmitted symbols over several antennas.Many different MIMO detector algorithms exist\r\nfor this spatialmultiplexing. The major difference between differentMIMOdetectors is the resulting communications performance\r\nand implementation complexity, respectively. Particularly closed-loop MIMO systems have attained a lot of attention in the last\r\nyears. In a closed-loop system, reliability information is fed back from the channel decoder to the MIMO detector. In this paper, we\r\nderive a basic framework to compare different soft-input soft-output MIMO detectors in open- and closed-loop systems. Within\r\nthis framework, we analyze a depth-first sphere detector and a breadth-first fixed effort detector for different application scenarios\r\nand their effects on area and energy efficiency on the whole system.We present all system components under open- and closed-loop\r\nsystem aspects and determine the overall implementation cost for changing an open-loop system in a closed-loop system....
The power consumption is an important factor in communication and embedded system applications. The power consumption of any device can be reduced, only when there is reduction in static and dynamic power consumption .The performance of the circuit is also degraded due to minimising the power supply requirement. This paper reports on the design of a phase-locked-loop (PLL) for on-chip clock generation for a high-performance application. The power consumption of the applications has been reduced by scaling down the supply voltage. The whole system has been implemented using a 1.25um CMOS process that features low-threshold voltages for MOS devices to maintain the speed performance....
The complexity of timing optimization of high-performance circuits has been increasing rapidly in proportion to the shrinking\r\nCMOS device size and rising magnitude of process variations. Addressing these significant challenges, this paper presents a\r\ntiming optimization algorithm for CMOS dynamic logic and a Path Oriented IN Time (POINT) optimization flow for mixedstatic-\r\ndynamic CMOS logic, where a design is partitioned into static and dynamic circuits. Implemented on a 64-b adder and\r\nInternational Symposium on Circuits and Systems (ISCAS) benchmark circuits, the POINT optimization algorithm has shown an\r\naverage improvement in delay by 38% and delay uncertainty from process variations by 35% in comparison with a state-of-the-art\r\ncommercial optimization tool....
Power and area efficient multiplier using CMOS logic circuits for applications in various digital signal processors is designed. This multiplier is implemented using Vedic multiplication algorithms mainly the \"Urdhvatiryakbhyam sutra\" , which is the most generalized one Vedic multiplication algorithm [1] . A multiplier is a very important element in almost all the processors and contributes substantially to the total power consumption of the system. The novel point is the efficient use of Vedic algorithm (sutras) that reduces the number of computational steps considerably compared with any conventional method . The schematic for this multiplier is designed using TANNER TOOL. The design is then verified in T-SPICE using 0.18 um CMOS technology library file. The analysis is made for various voltages across a range of 2.5V to 5V, to validate the design. A CMOS digital multiplier, with low power consumption and high linearity is proposed. The results prove that the proposed multiplier consumes 80% less power compared to the gate level analysis done earlier. The core area of the proposed multiplier is 737 um2 . Paper presents a systematic design methodology for this improved performance digital multiplier based on Vedic mathematics....
Application Specific Instruction-set Processors (ASIPs) expose to the designer a large number of degrees of freedom. Accurate and\r\nrapid simulation tools are needed to explore the design space. To this aim, FPGA-based emulators have recently been proposed\r\nas an alternative to pure software cycle-accurate simulator. However, the advantages of on-hardware emulation are reduced by\r\nthe overhead of the RTL synthesis process that needs to be run for each configuration to be emulated. The work presented in\r\nthis paper aims at mitigating this overhead, exploiting a form of software-driven platform runtime reconfiguration. We present\r\na complete emulation toolchain that, given a set of candidate ASIP configurations, identifies and builds an overdimensioned\r\narchitecture capable of being reconfigured via software at runtime, emulating all the design space points under evaluation. The\r\napproach has been validated against two different case studies, a filtering kernel and an M-JPEG encoding kernel. Moreover, the\r\npresented emulation toolchain couples FPGA emulation with activity-based physical modeling to extract area and power/energy\r\nconsumption figures. We show how the adoption of the presented toolchain reduces significantly the design space exploration\r\ntime, while introducing an overhead lower than 10% for the FPGA resources and lower than 0.5% in terms of operating frequency....
A high-speed low-complexity hardware interleaver/deinterleaver is presented. It supports all 77 802.11n high-throughput (HT)\r\nmodulation and coding schemes (MCSs) with short and long guard intervals and the 8 non-HT MCSs defined in 802.11a/g.\r\nThe paper proposes a design methodology that distributes the three permutations of an interleaver to both write address and\r\nread address. The methodology not only reduces the critical path delay but also facilitates the address generation. In addition,\r\nthe complex mathematical formulas are replaced with optimized hardware structures in which hardware intensive dividers and\r\nmultipliers are avoided. Using 0.13um CMOS technology, the cell area of the proposed interleaver/deinterleaver is 0.07mm2, and\r\nthe synthesized maximal working frequency is 400 MHz. Comparison results show that it outperforms the three other similar\r\nworks with respect to hardware complexity and max frequency while maintaining high flexibility....
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