Current Issue : April-June Volume : 2022 Issue Number : 2 Articles : 5 Articles
This paper presents a 10 bit 100 MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) without calibration for industrial control system (ICS) applications. Several techniques are adopted in the proposed switching procedure to achieve better linearity, power and area efficiency. A single-side-fixed technique is utilized to reduce the number of capacitors; a parallel split capacitor array in combination with a partially thermometer coded technique can minimize the switching energy, improve speed, and decrease differential non-linearity (DNL). In addition, a compact timing-protection scheme is proposed to ensure the stability of the asynchronous SAR ADC. The proposed ADC is fabricated in a 28 nm CMOS process with an active area of 0.026 mm2. At 100 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 51.54 dB and a spurious free dynamic range (SFDR) of 55.12 dB with the Nyquist input. The measured DNL and integral non-linearity (INL) without calibration are +0.37/0.44 and +0.48/0.63 LSB, respectively. The power consumption is 1.1 mW with a supply voltage of 0.9 V, leading to a figure of merit (FoM) of 35.6 fJ/conversion-step....
In this work, a multi-independent-output, multi-string, high-efficiency, boost-converterbased white LED (WLED) driver architecture is proposed. It utilizes a single inductor main switch with a common maximum duty cycle controller (MDCC) in the feedback loop. A simple pulse skipping controller (PSC) is utilized in each high-side switch of the multiple independent outputs. Despite the presence of multiple independent outputs, a single over-voltage protection (OVP) circuit is used at the output to protect the circuit from any voltage above 27 V. An open circuit in any of the strings is addressed, in addition to the LED’s short-circuit conditions. Excellent current matching between strings is achieved, despite the low ON-resistance (Rdson) of transistors used in the 40 nm process. Most circuits are designed in digital CMOS logic to overcome the extreme process variations in the 40 nm node. Compared to a single output parallel strings topology, a 50% improvement in efficiency is achieved relative to extremely unbalanced strings. Three strings are used in this proposal, but more strings can be supported with the same topology. Each string is driven by a 25 mA current sink. An input voltage of 3.2–4.2 V and an output voltage up to 27 V are supported....
,is research proposed the design and calculations of ultra-low power (ULP) Doherty power amplifier (PA) using 65nm CMOS technology. Both the main and the peaking amplifiers are designed and optimized using equivalent lumped parameters and power combiner models. ,e operation has been performed in RF-nMOS subthreshold or triode region to achieve ultra-low power (ULP) and to improve the linearity of the overall power amplifier (PA). ,enovel design consumes a DC power of 2.1mW, poweradded efficiency (PAE) of 29.8%, operating at 2.4 GHz band, and output referred 1 dB compression point at 4.1dBm. ,e simulation results show a very good capability of drive current, high gain, and very low input and output insertion losses....
In this paper, guidelines for the optimization of piezoelectrical micromachined ultrasound transducers (PMUTs) monolithically integrated over a CMOS technology are developed. Higher acoustic pressure is produced by PMUTs with a thin layer of AlN piezoelectrical material and Si3N4 as a passive layer, as is studied here with finite element modeling (FEM) simulations and experimental characterization. Due to the thin layers used, parameters such as residual stress become relevant as they produce a buckled structure. It has been reported that the buckling of the membrane due to residual stress, in general, reduces the coupling factor and consequently degrades the efficiency of the acoustic pressure production. In this paper, we show that this buckling can be beneficial and that the fabricated PMUTs exhibit enhanced performance depending on the placement of the electrodes. This behavior was demonstrated experimentally and through FEM. The acoustic characterization of the fabricated PMUTs shows the enhancement of the PMUT performance as a transmitter (with 5 kPa V1 surface pressure for a single PMUT) and as a receiver (12.5 V MPa1) in comparison with previously reported devices using the same MEMS-on-CMOS technology as well as state-of-the-art devices....
The fin field-effect transistor (FinFET) has been the mainstream technology on the VLSI platform since the 22 nm node. The silicon-on-insulator (SOI) FinFET, featuring low power consumption, superior computational power and high single-event effect (SEE) resistance, shows advantages in integrated circuits for space applications. In this work, a rad-hard design methodology for SOI FinFETs is shown to improve the devices’ tolerance against the Total Ionizing Dose (TID) effect. Since the fin height direction enables a new dimension for design optimization, a 3D Source/Drain (S/D) design combined with a gate dielectric de-footing technique, which has been readily developed for the 14 nm node FinFETs, is proposed as an effective method for SOI FinFETs’ TID hardening. More importantly, the governing mechanism is thoroughly investigated using fully calibrated technology computer-aided design (TCAD) simulations to guide design optimizations. The analysis demonstrates that the 3D rad-hard design can modulate the leakage path in 14 nm node n-type SOI FinFETs, effectively suppress the transistors’ sensitivity to the TID charge and reduce the threshold voltage shift by >2. Furthermore, the rad-hard design can reduce the electric field in the BOX region and lower its charge capture rate under radiation, further improving the transistor’s robustness....
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