Current Issue : April-June Volume : 2022 Issue Number : 2 Articles : 5 Articles
Real-time object detection is a challenging but crucial task for autonomous underwater vehicles because of the complex underwater imaging environment. Resulted by suspended particles scattering and wavelength-dependent light attenuation, underwater images are always hazy and color-distorted. To overcome the difficulties caused by these problems to underwater object detection, an end-to-end CNN network combined U-Net and MobileNetV3-SSDLite is proposed. Furthermore, the FPGA implementation of various convolution in the proposed network is optimized based on the Winograd algorithm. An efficient upsampling engine is presented, and the FPGA implementation of squeeze-and-excitation module in MobileNetV3 is optimized. The accelerator is implemented on a Zynq XC7Z045 device running at 150 MHz and achieves 23.68 frames per second (fps) and 33.14 fps when using MobileNetV3-Large and MobileNetV3-Small as the feature extractor. Compared to CPU, our accelerator achieves 7.5–8.7 speedup and 52–60 energy efficiency....
For the most extensive range of tasks, such as real-time data processing in intelligent transport systems, etc., advanced computer-based techniques are required. They include fieldprogrammable gate arrays (FPGAs). This paper proposes a method of pre-calculating the hardware complexity of computing a group of polynomial functions depending on the number of input variables of the said functions, based on the microchips of FPGAs. These assessments are reduced for a group of polynomial functions due to computing the common values of elementary polynomials. Implementation is performed using similar software IP-cores adapted to the architecture of userprogrammable logic arrays. The architecture of FPGAs includes lookup tables and D flip-flops. This circumstance ensures that the pipelined data processing provides the highest operating speed of a device, which implements the group of polynomial functions defined over a Galois field, independently of the number of variables of the said functions. A group of polynomial functions is computed based on common variables. Therefore, the input/output blocks of FPGAs are not a significant limiting factor for the hardware complexity estimates. Estimates obtained in using the method proposed allow evaluating the amount of the reconfigurable resources of FPGAs, required for implementing a group of polynomial functions defined over a Galois field. This refers to both the existing FPGAs and promising ones that have not yet been implemented....
Convolutional neural networks (CNNs) are widely used in modern applications for their versatility and high classification accuracy. Field-programmable gate arrays (FPGAs) are considered to be suitable platforms for CNNs based on their high performance, rapid development, and reconfigurability. Although many studies have proposed methods for implementing highperformance CNN accelerators on FPGAs using optimized data types and algorithm transformations, accelerators can be optimized further by investigating more efficient uses of FPGA resources. In this paper, we propose an FPGA-based CNN accelerator using multiple approximate accumulation units based on a fixed-point data type. We implemented the LeNet-5 CNN architecture, which performs classification of handwritten digits using the MNIST handwritten digit dataset. The proposed accelerator was implemented, using a high-level synthesis tool on a Xilinx FPGA. The proposed accelerator applies an optimized fixed-point data type and loop parallelization to improve performance. Approximate operation units are implemented using FPGA logic resources instead of high-precision digital signal processing (DSP) blocks, which are inefficient for low-precision data. Our accelerator model achieves 66% less memory usage and approximately 50% reduced network latency, compared to a floating point design and its resource utilization is optimized to use 78% fewer DSP blocks, compared to general fixed-point designs....
In this study, a novel control approach for a doubly-fed induction generator (DFIG) is developed and applied to improve the system’s dynamic response and performance for providing high energy quality while avoiding harmonic accumulations. Because of its ease of implementation, field-oriented control (FOC) is frequently used. This control has great sensitivity to the machine’s parametric variations. For this reason, adaptive Backstepping control (ABC) is capable of preserving almost all of the performance and robustness properties. However, its analytical formulation has a problem. To overcome these disadvantages, the hybrid control (HC) is developed and verified to enable rapid response, complete reference tracking, and appropriate dynamic behavior with a low ripple level. This control is a combination of FOC’s and ABC’s control laws. The prepared control is explored by simulation testing using Matlab/Simulink and practical implementation using an FPGA board with actual turbine settings and a real wind profile of Dakhla City, Morocco. The results of hardware simulation show the efficacy of the HC in terms of speed and robustness, with a total harmonic distortion THD = 0.95, a value of THD that reveals the quality of the energy injected into the grid....
Reconfigurable intelligent surface (RIS) is considered to be a new technology with great potential and is being studied extensively and deeply. And the application extension of STBC in the RIS-aided scheme provides a new train of thought for the research of channel coding. In this paper, we propose we extend the scheme of using the RIS to adjust the phase and reconfigure the reflected signal and propose the design of the RIS-aided QO-STBC scheme and the RIS-aided QO-STBC scheme with interference cancellation. Particularly in the RIS-aided QO-STBC scheme with interference cancellation, the design can achieve the transmission of the full rate and full diversity using an auxiliary reflection group to eliminate the influence of interference term. Also, the advantages and disadvantages of the schemes are analyzed in the paper, and the decoding algorithms with different complexity used in the proposed schemes are described. The simulation results show that the performance of the RISaided QO-STBC scheme with interference cancellation is better than that of the RIS-aided QO-STBC scheme and the RISaided Alamouti scheme by about 5 dB and 7 dB at 10−3 BER because of diversity gain and coding gain....
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