Current Issue : July-September Volume : 2022 Issue Number : 3 Articles : 5 Articles
In this article, we present the design, fabrication, and characterization of a thermopile infrared sensor array (TISA) pixel. This TISA pixel is composed of a dual-layer p+/n poly-Si thermopile with a closed membrane and an n-channel metal oxide semiconductor (NMOS) switch. To address the challenges in fabrication through the 3D integration method, the anode of the thermopile is connected to the drain of the NMOS, both of which are fabricated on the same bulk wafer using a CMOS compatible monolithic integration process. During a single process sequence, deposition, etching, lithography, and ion implantation steps are appropriately combined to fabricate the thermopile and the NMOS simultaneously. At the same time as ensuring high thermoelectric characteristics of the dual-layer p+/n poly-Si thermopile, the basic switching functions of NMOS are achieved. Compared with a separate thermopile, the experimental results show that the thermopile integrated with the NMOS maintains a quick response, high sensitivity and high reliability. In addition, the NMOS employed as a switch can effectively and quickly control the readout of the thermopile sensing signal through the voltage, both on and off, at the gate of NMOS. Thus, such a TISA pixel fabricated by the monolithic CMOS-compatible integration approach is low-cost and highperformance, and can be applied in arrays for high-volume production....
The design of the analog baseband circuit is based on 55 nm CMOS technology and is integrated in an IEEE 802.11ax concurrent dual band four antenna transceiver. A low-pass filter (LPF) of the receiver was multiplexed with an LPF-transmitter such that the last three stages of the fifth order LPF-receiver were used by the LPF-transmitter, and the first programmable gain amplifier (PGA) of the receiver was partially multiplexed with the PGA-transmitter such that the PGA-receiver and the PGA-transmitter shared the same operational amplifier and input resistance, thereby reducing the power consumption, noise, linearity, and area of intermediate frequency (IF) of the transmitter designed separately. The typical bandwidth of the IF-receiver is 10/20/40 MHz; that of the IF-transmitter is 12/24/50 MHz. The gain range of the IF-receiver and the IF-transmitter is 0.1–65.5 dB and 10.1 to 3.98 dB, respectively. Under the voltage of 1.5 V, the current of the IF-receiver is 3.86 mA. As for the IF-transmitter, the current is 1.78 mA when supply voltage is 1.5 V. The input referred noise (IRN) of the IF-receiver at 10 MHz bandwidth (BW) and 62 dB gain is 14.52 nV/ p Hz, while the IRN of the IF-transmitter at 10 MHz BW and 6 dB gain is 95.16 nV/ p Hz. The suppression ability of the DC offset cancellation circuit is 35.08/80.9/110.1/113 dB. The area of the analog baseband circuit is 0.17 mm2....
Today, an electron spin qubit on silicon appears to be a very promising physical platform for the fabrication of future quantum microprocessors. Thousands of these qubits should be packed together into one single silicon die in order to break the quantum supremacy barrier. Microelectronics engineers are currently leveraging on the current CMOS technology to design the manipulation and read-out electronics as cryogenic integrated circuits. Several of these circuits are RFICs, as VCO, LNA, and mixers. Therefore, the availability of a qubit CAD model plays a central role in the proper design of these cryogenic RFICs. The present paper reports on a circuit-based compact model of an electron spin qubit for CAD applications. The proposed model is described and tested, and the limitations faced are highlighted and discussed....
In this paper we investigate the performance of an integrated n-type laterally-diffused metal oxide semiconductor (nLDMOS) transistor, using 2D TCAD simulations. This work is based on the 1 μm CMOS technology node at CDTAs clean room. The nLDMOS process uses the necessary steps extracted from logic-integrated circuits fabrication flow, which yields to local oxidation of silicon (LOCOS), single reduced surface field (RESURF)-based nLDMOS, without needing any additional masks or steps. The resulting device has a 22 V breakdown voltage (BV) and 272 mm2 mΩ specific on-state resistance (RON). The analysis determined that the proposed device could be implemented in RF power amplifiers for wireless communications or automotive circuits as primary domains, provided experimental calibrations....
In this work, the electrostatic discharge (ESD) characteristics of a pMOS-triggered bidirectional silicon-controlled rectifier (PTBSCR) that was fabricated in a 0.18 μm silicon-oninsulator (SOI) bipolar-CMOS-DMOS (BCD) process, is investigated. The multi-snapback phenomenon was observed under the transmission line pulsing (TLP) test system. It was found that gate voltage and inserting shallow trench isolation (STI) can significantly affect the trigger voltage and holding voltage. The underlying physical mechanism related to the multi-snapback phenomenon and the effects of gate voltage on the critical parameters was investigated through the experimental results and the assistance of technology computer-aided design (TCAD) simulations. The adjustments of gate voltage and STI on the critical ESD parameters of the device provide an effective design idea for low-voltage ESD protection in the SOI BCD process....
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