Current Issue : July - September Volume : 2012 Issue Number : 3 Articles : 4 Articles
The need for ultra low power circuits has forced circuit designers to scale\r\nvoltage supplies into the sub-threshold region where energy per operation is minimized [1].\r\nThe problem with this is that the traditional 6T SRAM bitcell, used for data storage,\r\nbecomes unreliable at voltages below about 700 mV due to process variations and\r\ndecreased device drive strength [2]. In order to achieve reliable operation, new bitcell\r\ntopologies and assist methods have been proposed. This paper provides a comparison of\r\nfour different bitcell topologies using read and write VMIN as the metrics for evaluation. In\r\naddition, read and write assist methods were tested using the periphery voltage scaling\r\ntechniques discussed in [4ââ?¬â??13]. Measurements taken from a 180 nm test chip show read\r\nfunctionality (without assist methods) down to 500 mV and write functionality down to\r\n600 mV. Using assist methods can reduce both read and write VMIN by 100 mV over the\r\nunassisted test case....
Minimizing power consumption during functional operation and during\r\nmanufacturing tests has become one of the dominant requirements for the semiconductor\r\ndesigns in the past decade. From commercial design-for-test (DFT) tools� point of view,\r\nthis paper describes how DFT tools can help to achieve comprehensive testing of low\r\npower designs and reduce test power consumption during test application....
One of the major power consuming components in a computer is its display unit.\r\nOn average the screen consumes ten times more power than the DSP processor itself. Thus,\r\nreducing the power consumption should be one of the most important tasks in the\r\ndevelopment of low power consumption computing systems. In this paper we present one\r\npossible solution involving micro projection device based upon lasers and a digital light\r\nprocessing (DLP) matrix which is a matrix of electrically controllable mirrors capable of\r\ntranslating electrical signal to a time varying projected image. It can serve to substitute\r\na screen and consume ten times less power than a conventional screen. The described\r\ndevice is a multifunctional highly efficient customized DLP light engine being capable\r\nof serving as an image projector and simultaneously to support range and topography\r\nestimation measurements....
A low complexity digital VLSI architecture for the computation of an algebraic\r\ninteger (AI) based 8-point Arai DCT algorithm is proposed. AI encoding schemes for\r\nexact representation of the Arai DCT transform based on a particularly sparse 2-D AI\r\nrepresentation is reviewed, leading to the proposed novel architecture based on a new final\r\nreconstruction step (FRS) having lower complexity and higher accuracy compared to the\r\nstate-of-the-art. This FRS is based on an optimization derived from expansion factors that\r\nleads to small integer constant-coefficient multiplications, which are realized with common\r\nsub-expression elimination (CSE) and Booth encoding. The reference circuit [1] as well\r\nas the proposed architectures for two expansion factors a�= 4.5958 and a = 167.2309\r\nare implemented. The proposed circuits show 150% and 300% improvements in the\r\nnumber of DCT coefficients having error =0.1% compared to [1]. The three designs were\r\nrealized using both 40 nm CMOS Xilinx Virtex-6 FPGAs and synthesized using 65 nm\r\nCMOS general purpose standard cells from TSMC. Post synthesis timing analysis of 65 nm\r\nCMOS realizations at 900 mV for all three designs of the 8-point DCT core for 8-bit inputsshow potential real-time operation at 2.083 GHz clock frequency leading to a combined\r\nthroughput of 2.083 billion 8-point Arai DCTs per second. The expansion-factor designs\r\nshow a 43% reduction in area (A) and 29% reduction in dynamic power (PD) for FPGA\r\nrealizations. An 11% reduction in area is observed for the ASIC design for a�= 4.5958\r\nfor an 8% reduction in total power (PT ). Our second ASIC design having a = 167.2309\r\nshows marginal improvements in area and power compared to our reference design but at\r\nsignificantly better accuracy...
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