Current Issue : October-December Volume : 2022 Issue Number : 4 Articles : 5 Articles
This article describes an asynchronous split-CDAC-based SAR ADC with integrated input PGA and an RV-Buffer. The split CDAC structure not only reduces the area of the ADC, but also relieves the driving pressure of the input PGA and RV-Buffer. Using the input PGA instead of the traditional input buffer as the driving circuit of the ADC increases the dynamic input range of the ADC. The proposed on-chip RV-Buffer can provide 1.1 V positive and 0.1 V negative voltage, avoiding the disturbance caused by off-chip reference. This prototype is implemented in a 65 nm CMOS process and occupies an active area of 0.088 mm2. The input PGA can provide 0–18 dB programmable gain with a step of 3 dB. Measurement results show that as the provided gain changes, the ADC’s SNR is best, reaching 50.9 dB, and the SFDR is beat, reaching 62.35 dB at 50 MS/s....
This paper presents a differential 19.6–39.4 GHz broadband low-noise amplifier (LNA) in 65-nm CMOS technology. The LNA consists of two cascode stage and one common-source stage. To achieve a wide bandwidth and low average noise figure, inter-stage peak-gain distribution technique and transformer-based triple-coupled technique are developed. Besides, a new compact T-coil-based network is proposed to neutralize the parasitic capacitors and enlarge the gain. The measure results show that the 3-dB bandwidth is from 19.6 to 39.4 GHz, the maximum gain is 23.5 dB, and the noise figure (NF) is from 3.7 to 5.8 dB. The dc power comsumption is 46 mW with 1V supply voltage. The input P1dB is −17 dBm at 30 GHz....
In this article, a dual-loop dual-output frequency synthesizer designed for IEEE802.11aj (45 GHz) standard is presented. In order to support the super-heterodyne transceiver, the Loop1 output frequency is fixed for easy design of high-performance IF transceiver and filter, and the Loop2 output frequency varies for the channel selection according to the IEEE802.11aj (45 GHz) standard. The power hungry high-speed prescaler (or multi-modulus-divider) is replaced with a mixer in Loop2, thus the in-band phase noise and DC power consumption can be improved. The dual-loop dual-output synthesizer is fabricated in 0.13 μm SiGe BiCMOS technology, occupies an area of 2.7 mm × 2.4 mm, and consumes 610 mW DC power. Measured results show the phase noise of the frequency synthesizer are −79.3 dBc/Hz@10 kHz and −129.1 dBc/Hz@10 MHz at 12.96 GHz for Output1 and −76.6 dBc/Hz@10 kHz and −117.2 dBc/Hz@10 MHz at 32.535 GHz for Output2. The low-reference spur of −69.2 dBc and low-power level spurious tones at the outputs are observed during the measurement. To the best of our knowledge, this work is the first reported dual-loop dual-output synthesizer designed for IEEE802.11aj (45 GHz) standard....
In this article, ultrascaled junctionless (JL) field-effect phototransistors based on carbon nanotube/nanoribbons with sub-10 nm photogate lengths were computationally assessed using a rigorous quantum simulation. This latter self-consistently solves the Poisson equation with the mode space (MS) non-equilibrium Green’s function (NEGF) formalism in the ballistic limit. The adopted photosensing principle is based on the light-induced photovoltage, which alters the electrostatics of the carbon-based junctionless nano-phototransistors. The investigations included the photovoltage behavior, the I-V characteristics, the potential profile, the energy-position-resolved electron density, and the photosensitivity. In addition, the subthreshold swing–photosensitivity dependence as a function of change in carbon nanotube (graphene nanoribbon) diameter (width) was thoroughly analyzed while considering the electronic proprieties and the quantum physics in carbon nanotube/nanoribbon-based channels. As a result, the junctionless paradigm substantially boosted the photosensitivity and improved the scaling capability of both carbon phototransistors. Moreover, from the point of view of comparison, it was found that the junctionless graphene nanoribbon field-effect phototransistors exhibited higher photosensitivity and better scaling capability than the junctionless carbon nanotube field-effect phototransistors. The obtained results are promising for modern nano-optoelectronic devices, which are in dire need of high-performance ultra-miniature phototransistors....
In order to ensure the correct behaviors and that bugs have not entered the design, equivalence checking technology plays an important role in VLSI design. In this paper, we propose a new template-based, semi-formal equivalence checking method for C-based system design and Register Transfer Level (RTL)/netlist implementation design, whose internal structures can be very different. Staring with a C-based description as a specification, we first randomly generate a set of templates. Each template has one or a small number of missing sentences based on the original C description. Many sets of mutants can be represented by these templates, using symbolic constants, variables, and operators. The process of finding those missing portions can be formulated as a Quantified Boolean Formula (QBF) problem. Then, based on the counter-example guided method, by simulating only the implementation, the templates can be refined. Since the templates are generated from the original C description, their structures are very similar to each other. With the original C description as a specification, we can simulate or formally check the equivalence between the refined template and the original C description, thereby indirectly achieving the equivalence checking of the C-based systems design and RTL/netlist implementation design. The experimental results on several practical examples demonstrate the effectiveness of the proposed method....
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