Current Issue : April-June Volume : 2023 Issue Number : 2 Articles : 5 Articles
This paper presents an electrochemical impedance spectroscopy (EIS) system-on-chip in 0.18-μm CMOS, achieving a wide scan frequency range of 1.25 MHz. An on-chip direct digital frequency synthesizer generates a digital sine wave as well as in-phase and quadrature-phase clocks that are synchronized to the sinewave. A chopped sampling mixer realizes lock-in detection without requiring quadrature sinewaves while suppressing low-frequency noise and offset. The receive utilizes a 12-bit pipelined SAR ADC operating in 5 MS/s in combination with a digital averaging filter to maximize the dynamic range. The measured performance shows that the prototype EIS chip achieves the highest frequency scan range with a comparable dynamic range of 108 dB and power consumption of 14 mW when compared with the previous state-of-the-art prototypes....
In typical stimulated Raman scattering (SRS) signal extraction, the photodetector and lockin amplifier are often based on separate platforms, rendering the system cumbersome and non-scalable. This paper proposes an SRS double-demodulation lock-in amplifier implemented with a complementary metal-oxide semiconductor (CMOS) image sensor technology that integrates two-stage 1/f noise and offset reduction circuits with a high-speed lateral electric field modulation (LEFM) photo-demodulator. A weak SRS signal is buried in a large offset with a ratio of 104 to 106; boosting such signals in a CMOS device requires an extremely high offset and noise reduction capability. The double-modulation two-stage lock-in amplifier demodulates at 40 MHz with a sampling frequency of 20 MHz, can suppress the laser and circuit’s 1/f noise to achieve higher detection sensitivity. A prototype chip fabricated using 0.11 m CMOS image sensor technology is evaluated. Both simulation and measurement results are presented to verify the functionality and show that the differential readout structure can successfully reject laser common mode components while emphasizing its differences. The measurement results show that the double-modulation lock-in amplifier effectively suppresses the circuit’s 1/f noise by a factor of nearly two decades....
This paper presents a low-area 8-bit flash ADC that consumes low power. The flash ADC includes four main blocks—an analog multiplexer (MUX), a comparator, an encoder, and an SPI (Serial Peripheral Interface) block. The MUX allows the selection between eight analog inputs. The comparator block contains a TIQ (Threshold Inverter Quantization) comparator, a control circuit, and a proposed architecture of a Double-Tail (DT) comparator. The advantage of using the DT comparator is to reduce the number of comparators by half, which helps reduce the design area. The SPI block can provide a simple way for the ADC to interface with microcontrollers. This mixed-signal circuitry is designed and simulated using 180 nm CMOS technology. The 8-bit flash ADC only employs 128 comparators. The applied input clock is 80 MHz, with the input voltage ranging from 0.6 V to 1.8 V. The comparator block outputs 127 bits of thermometer code and sends them to the encoder, which exports the seven least significant bits (LSB) of the binary code. The most significant bit (MSB) is decided by only one DT comparator. The design consumes 2.81 mW of power on average. The total area of the layout is 0.088 mm2. The figure of merit (FOM) is about 877 fJ/step. The research ends up with a fabricated chip with the design inserted into it....
ITO/WOx/TaN and ITO/WOx/AlOx/TaN memory cells were fabricated as a neuromorphic device that is compatible with CMOS. They are suitable for the information age, which requires a large amount of data as next-generation memory. The device with a thin AlOx layer deposited by atomic layer deposition (ALD) has different electrical characteristics from the device without an AlOx layer. The low current is achieved by inserting an ultra-thin AlOx layer between the switching layer and the bottom electrode due to the tunneling barrier effect. Moreover, the short-term memory characteristics in bilayer devices are enhanced. The WOx/AlOx device returns to the HRS without a separate reset process or energy consumption. The amount of gradual current reduction could be controlled by interval time. In addition, it is possible to maintain LRS for a longer time by forming it to implement long-term memory....
A new improved accuracy CMOS Gaussian function generator will be presented. The original sixth-order approximation function that represents the basis for designing the proposed Gaussian circuit allows a large increase in the circuit accuracy and also of the input variable maximal range. The original proposed computational structure has a large dynamic output range of 27 dB, for a variation smaller than 1 dB as compared with the ideal Gaussian function. The circuit is simulated for 0.18 m CMOS technology and has a low supply voltage (VDD = 0.7 V). Its power consumption is smaller than 0.22 W, for VDD = 0.7 V, while the chip area is about 7 m2. The new proposed architecture is re-configurable, the convenient modification of the coefficients allowing to obtain many mathematical functions using the same computational structure....
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