Current Issue : July-September Volume : 2023 Issue Number : 3 Articles : 5 Articles
Combining with a static random-access memory (SRAM) and resistive memory (RRAM), an improved 8T2R nonvolatile SRAM (nvSRAM) memory cell is proposed in this study. With differential mode, a pair of 1T1R RRAM is added to 6T SRAM storage node. By optimizing the connection and layout scheme, the power consumption is reduced and the data stability is improved. The nvSRAM memory cell is realized with UMC CMOS 28nm 1p9m process. When the power supply voltage is 0.9 V, the static noise/ read/write margin is 0.35 V, 0.16 V, and 0.41 V, respectively. The data storage/restoration time is 0.21 ns and 0.18 ns, respectively, with an active area of 0.97 μm2....
The current trend of increasing the complexity of hardware accelerators to improve their functionality is highlighting the problem of sharing a high-frequency clock signal for all integrated modules. As the clock itself is becoming the main limitation to the performance of accelerators, in this manuscript, we present the design of an asymmetric Ring Oscillator-Voltage-Controlled Oscillator (RO-VCO) based on the CurrentMode Logic architecture. The RO-VCO was designed on commercialgrade 65 nm CMOS technology, and it is capable of driving large capacitance loads, avoiding the need for additional buffers for clock-trees, reducing the silicon area and power consumption. The proposed RO-VCO is composed of three closed-loop differential and asymmetrical stages, and it is able to tune the working frequency in the range from 4.72 GHz to 6.12 GHz. The phase noise and a figure of merit of −103.2 dBc/Hz and −186 dBc/Hz were obtained at 1 MHz offset from the 5.5 GHz carrier. In this article, the analytical model, full custom schematic, and layout of the proposed RO-VCO are presented and discussed in detail together with the experimental electrical and thermal characterization of the fabricated device....
In this paper, an optimized memristor emulator circuit is designed, by using nine MOSFET transistors and a ground capacitor. Our area- and power-optimized emulator circuit can be used for basic data storage and processing at the monitoring edge, in real-time applications. The memristor shows a nonlinear voltage–current relationship, but no multiplier circuit provides the memristor’s nonlinear characteristics. As a result, the proposed memristor emulator has a very low chip area. The memristor circuit is designed in LTSpice, using 16 nm and 45 nm CMOS technology parameters, and the operating voltage is ±0.9 V. In this research, the theoretical derivations are validated using the simulated results of the memristor emulator circuit using different frequencies, capacitors, and input voltages in SPICE simulations....
The QC-LDPC code, with its excellent error correction performance and hardware friendliness, has been identified as one of the channel encoding schemes byWi-Fi 6. Shorting, puncturing, or repeating operations are needed to ensure that user data can be sent with integer symbols and complete rate matching. Due to the uncertainty of the user data size, the modulation’s selectivity, and the difference in the number of spatial streams, the receiver must deal with more than 106 situations. At the same time, other computationally intensive tasks occupy the time slot budget of the receiver. Typical are demodulation and decoding. Hence, the receiver needs to quickly reverse the demodulated data process. This paper first proposes a co-processing method and VLSI architecture compatible with all code lengths, code rates, and processing parameters. The co-processor separates field and block splicing, simplifying the control logic. There is no throughput rate bottleneck, and the maximum delay is less than 1 us....
The threshold voltage distribution technique is an effective way to reduce the static power consumption of integrated circuits. Several gate-level-based distribution algorithms have been proposed, but the optimization effect and run time still need further optimization when applied to very large-scale integration (VLSI) designs. This paper presents a triple-threshold path-based static power optimization methodology (TPSPOM) for low-power system-on-chip. This method obtains the path weights and cell weights from paths’ timing constraints and cells’ delay-to-power ratios, then uses them as indexes to distribute each cell to low-threshold voltage (LVT), standard-threshold voltage (SVT), or high-threshold voltage (HVT). The experimental results based on a 28 nm circuit containing 385,781 cells show that the TPSPOM method reduces static power consumption by 15.16% more than the critical-path aware power consumption optimization methodology (CAPCOM). At the same time, run time is reduced by 96.85%....
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