Current Issue : October-December Volume : 2023 Issue Number : 4 Articles : 5 Articles
This paper presents a small-size broadband slot monopole chip antenna for millimeter wave application. Using a 0.18 μm CMOS process, through metal_1, the artificial magnetic conductor (AMC) of the metal layer increased the impedance bandwidth of the chip antenna. The additional inverted C branch was used to achieve a better reflection coefficient. By adding an AMC and inverted C branch, the operating frequency of the chip antenna went to 33.8–110 GHz below the reflection coefficient of −10 dB, and its fractional bandwidth was 103.4%. The maximum gain was −6.3 dBi at 72 GHz. The overall chip size was 1.2 × 1.2 (mm2). Through measurement and verification, the proposed antenna reflection coefficient was close to the simulation trend and had better resonance. The frequency range of the chip antenna proposed in this paper covered the 5G NR FR2 band (24.2 GHz–52.6 GHz) and W-band (75 GHz–110 GHz). The proposed chip antenna can be applied to the Internet of Things, Industry 4.0, biomedical electronics, near field sensing and other related fields....
A novel split-gate SiC MOSFET with an embedded MOS-channel diode for enhanced third-quadrant and switching performances is proposed and studied using TCAD simulations in this paper. During the freewheeling period, the MOS-channel diode with a low potential barrier constrains the reverse current flow through it. Therefore, the suggested device not only has a low diode cut-in voltage but also entirely suppresses the intrinsic body diode, which will cause bipolar deterioration. In order to clarify the barrier-lowering effect of the MOS-channel diode, an analytical model is proposed. The calibrated simulation results demonstrate that the diode cut-in voltage of the proposed device is decreased from the conventional voltage of 2.7 V to 1.2 V. In addition, due to the split-gate structure, the gate-to-drain charge (QGD) of the proposed device is 20 nC/cm2, and the reverse-transfer capacitance (CGD) is 14 pF/cm2, which are lower than the QGD of 230 nC/cm2 and the CGD of 105 pF/cm2 for the conventional one. Therefore, a better high-frequency figure-of-merit and lower switching loss are obtained....
In this paper, we propose a new hardware algorithm for an integer based discrete cosine transform (IntDCT) that was designed to allow an efficient VLSI implementation of the discrete cosine transform using the systolic array architectural paradigm. The proposed algorithm demonstrates multiple benefits specific to integer transforms with efficient hardware implementation and sufficient precision in approximating irrational transform coefficients for practical applications. The proposed integer DCT algorithm can be efficiently restructured into five regular and modular computational structures of lengths of four and one of length two called pseudo-cycle convolutions which translate into efficient VLSI implementations using systolic arrays. Moreover, besides an efficient VLSI implementation with high-speed performances due to the parallel decomposition of the proposed integer DCT algorithm, the proposed VLSI architecture uses a tag control mechanism that facilitates the integration of an obfuscation technique that significantly improves the hardware security with low overheads, maintaining all the implementation performances....
In this paper, for the wireless network, wearable device, and Internet of Things (IoT) markets, a delay-locked loop (DLL) is used to implement accurate multiplication for a reference clock and the frequency of various applications through an edge combiner (EC). A simpler structure is more sensitive to process, voltage, and temperature (PVT), so DLL complements itself quickly in the feedback system and improves the stability of the final output. The proposed DLL-based multiplier can prevent harmonic lock generation using a first phase canceller (FPC), thus compensating for faster lock time. The circuit is built with a 55 nm CMOS process and has a chip area of 0.0225 mm2. The proposed design achieves a total power consumption of 0.48 mW at the 30.72 MHz operating clock frequency, and the clock duty can also operate stably from 15 to 75%....
High-energy particles in space often induce single event effects in CMOS image sensors, resulting in performance degradation and functional failure. This paper focuses on the formation and morphology of transient bright spots in CMOS image sensors and analyzes the formation process of transient bright spots by conducting heavy ion irradiation experiments to obtain the variation law of transient bright spots with heavy ion linear energy transfer values and background gray values; in addition, we classify the single event upset that occurred in the experiments according to the state of transient bright spots and extract the characteristics of different single event upsets. The failure mechanisms of different single event upsets are analyzed according to their characteristics and are combined with the information given by transient bright spots. This provides an essential reference for rapidly evaluating single event effects and the reinforcement design of CMOS image sensors....
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