Current Issue : April-June Volume : 2024 Issue Number : 2 Articles : 5 Articles
We report a milestone in achieving large-scale, ultrathin (~5 nm) superconducting NbN thin films on 300 mm Si wafers using a high-volume manufacturing (HVM) industrial physical vapor deposition (PVD) system. The NbN thin films possess remarkable structural uniformity and consistently high superconducting quality across the entire 300 mm Si wafer, by incorporating an AlN buffer layer. High-resolution X-ray diffraction and transmission electron microscopy analyses unveiled enhanced crystallinity of (111)-oriented δ-phase NbN with the AlN buffer layer. Notably, NbN films deposited on AlN-buffered Si substrates exhibited a significantly elevated superconducting critical temperature (~2 K higher for the 10 nm NbN) and a higher upper critical magnetic field or Hc2 (34.06 T boost in Hc2 for the 50 nm NbN) in comparison with those without AlN. These findings present a promising pathway for the integration of quantum-grade superconducting NbN films with the existing 300 mm CMOS Si platform for quantum information applications....
We present a 320 × 240 CMOS image sensor (CIS) using the proposed hybrid-correlated multiple sampling (HMS) technique with an adaptive dual-gain analog-to-digital converter (ADC). The proposed HMS improves the noise characteristics under low illumination by adjusting the ADC gain according to the incident light on the pixels. Depending on whether it is less than or greater than 1/4 of the full output voltage range from pixels, either correlated multiple sampling or conventional-correlated double sampling (CDS) is used with different slopes of the ramping signals. The proposed CIS achieves 11-bit resolution of the ADC using an up-down counter that controls the LSB depending on the ramping signals used. The sensor was fabricated using a 0.11 μm CIS process, and the total chip area was 2.55 mm × 4.3 mm. Compared to the conventional CDS, the measurement results showed that the maximum dark random noise was reduced by 26.7% with the proposed HMS, and the maximum figure of merit was improved by 49.1%. The total power consumption was 5.1 mW at 19 frames per second with analog, pixel, and digital supply voltages of 3.3 V, 3.3 V, and 1.5 V, respectively....
This paper presents an electron multiplication charge coupled device (EMCCD) based on capacitive deep trench isolation (CDTI) and developed using complementary metal oxide semiconductor (CMOS) technology. The CDTI transfer register offers a charge transfer inefficiency lower than 10−4 and a low dark current o 0.11 nA/cm2 at room temperature. In this work, the timing diagram is adapted to use this CDTI transfer register in an electron multiplication mode. The results highlight some limitations of this device in such an EM configuration: for instance, an unexpected increase in the dark current is observed. A design modification is then proposed to overcome these limitations and rely on the addition of an electrode on the top of the register. Thus, this new device preserves the good transfer performance of the register while adding an electron multiplication function. Technology computer-aided design (TCAD) simulations in 2D and 3D are performed with this new design and reveal a very promising structure....
Image sensors such as single-photon avalanched diode (SPAD) arrays typically adopt in-pixel quenching and readout circuits, and the under-illumination first-stage readout circuits often employs high-threshold input/output (I/O) or thick-oxide metal-oxide-semiconductor field-effect transistors (MOSFETs). We have observed reliability issues with high-threshold n-channel MOSFETs when they are exposed to strong visible light. The specific stress conditions have been applied to observe the drain current (Id) variations as a function of gate voltage. The experimental results indicate that photo-induced hot electrons generate interface trap states, leading to Id degradation including increased off-state current (Ioff) and decreased on-state current (Ion). The increased Ioff further activates parasitic bipolar junction transistors (BJT). This reliability issue can be avoided by forming an inversion layer in the channel under appropriate bias conditions or by reducing the incident photon energy....
Previous studies have shown that the application of the M-coder in the H.264/AVC and H.265/HEVC video coding standards allows for highly parallel implementations without decreasing maximal frequencies. Although the primary limitation on throughput, originating from the range register update, can be eliminated, other limitations are associated with low register processing. Their negative impact is revealed at higher degrees of parallelism, leading to a gradual throughput saturation. This paper presents optimizations introduced to the generative hardware architecture to increase throughputs and hardware efficiencies. Firstly, it can process more than one bypass-mode subseries in one clock cycle. Secondly, aggregated contributions to the codestream are buffered before the low register update. Thirdly, the number of contributions used to update the low register in one clock cycle is decreased to save resources. Fourthly, the maximal one-clock-cycle renormalization shift of the low register is increased from 32 to 64 bit positions. As a result of these optimizations, the binary arithmetic coder, configured for series lengths of 27 and 2 symbols, increases the throughput from 18.37 to 37.42 symbols per clock cycle for high-quality H.265/HEVC compression. The logic consumption increases from 205.6k to 246.1k gates when synthesized on 90 nm TSMC technology. The design can operate at 570 MHz....
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