Current Issue : January - March Volume : 2013 Issue Number : 1 Articles : 5 Articles
Reports to date of GaN HEMTs subjected to forward gate bias stress include varied extents of degradation.We report an extremely\r\nrobust GaN HEMT technology that survivedââ?¬â?contrary to conventional wisdomââ?¬â?high forward gate bias (+6V) and current\r\n(>1.8 A/mm) for >17.5 hours exhibiting only a slight change in gate diode characteristic, little decrease in maximum drain current,\r\nwith only a 0.1 V positive threshold voltage shift, and, remarkably, a persisting breakdown voltage exceeding 200 V....
A novel T-shaped piezoelectric ZnO cantilever sensor for chem/bio-detection is designed and fabricated with MEMS technology.\r\nBy using Rayleigh-Ritz method, the fundamental resonant frequency formula of T-shaped cantilevers is deduced for the first time\r\nand is validated by simulation results and experimental results. From this formula, we can easily find the superiority of adopting\r\nT-shape for the cantilevers. The complete process of the cantilever sensor is then successfully developed. The cantilever sensor\r\nis actuated by a layer of high-quality ZnO film with preferred (002) orientation, which is evaluated by SEM and XRD. The key\r\nstep of the process is protecting the ZnO film from KOH etching by a novel and effective method, which has rarely appeared\r\nin the literature. Finally, this cantilever sensor is measured by a network analyzer, and it has a fundamental resonant frequency\r\nof 24.60 kHz. The cantilever sensor developed in this study illustrates the feasibility and potential for many miniaturized sensor\r\napplications....
Effects of gate stack engineering and thermal treatment on electrical and interfacial properties of Ti/Pt/HfO2/InAs metal insulator\r\nsemiconductor (MIS) capacitors were systematically evaluated in terms of transmission electron microscopy, energy dispersive\r\nX-ray spectroscopy, current-voltage, and capacitance-voltage characterizations. A 10 nm thick Pt metal effectively suppresses the\r\nformation of interfacial oxide, TiO2, between the Ti gate and HfO2 gate dielectric layer, enhancing the gate modulation on the\r\nsurface potential of InAs. An in situ HfO2 deposition onto the n-InAs channel with an interfacial layer (IL) of one-monolayer InP\r\nfollowed by a 300?C post-metal-anneal produces a high-quality HfO2/InAs interface and thus unravels the annoying Fermi-level\r\npinning, which is evidenced by the distinct capacitance dips in the high-/low-frequency C-V characteristics. The interface trap\r\nstates could be further suppressed by replacing the InP IL by an As-rich InAs, which is substantiated by a gate leakage reduction\r\nand a steep voltage-dependent depletion capacitance....
We present copper structures composed of multilayer, stacked inductors (MLSIs) with tens of micro-Henry inductance for use\r\nin low frequency (sub 100 MHz), power converter technology. Unique to this work is the introduction of single-level lithography\r\nover the traditional two-level approach to create each inductor layer. The result is a simplified fabrication process which results in\r\na reduction in the number of lithography steps per inductor (metal) layer and a reduction in the necessary alignment precision.\r\nAdditionally, we show that this fabrication process yields strong adhesion amongst the layers, since even after a postprocess\r\nabrasion technique at the inner diameter of the inductors, no shearing occurs and connectivity is preserved. In total, three separate\r\nstructures were fabricated using the single-level lithography approach, each with a three-layered, stacked inductor design but with\r\nvaried geometries. Measured values for each of the structures were extracted, and the following results were obtained: inductance\r\nvalues of 24.74, 17.25, and 24.74 �µH, self-resonances of 9.87, 5.72, and 10.58 MHz, and peak quality factors of 2.26, 2.05, and 4.6,\r\nrespectively. These values are in good agreement with the lumped parameter model presented....
Considering the variety of studies that have been reported in low-power designing era, the subthreshold design trend in Very\r\nLarge Scale Integrated (VLSI) circuits has experienced a significant development in recent years. Growing need for the lowest\r\npower consumption has been the primary motivation for increase in research in this area although other goals, such as lowest\r\nenergy delay production, have also been achieved through sub-threshold design. There are, however, few extensive studies that\r\nprovide a comprehensive design insight to catch up with the rapid pace and large-scale implementations of sub-threshold digital\r\ndesign methodology. This paper presents a complete review of recent studies in this field and explores all aspects of sub-threshold\r\ndesign methodology. Moreover, near-threshold design and low-power pipelining are also considered to provide a general review\r\nof sub-threshold applications. At the end, a discussion about future directions in ultralow-power design is also included....
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