Current Issue : July - September Volume : 2013 Issue Number : 3 Articles : 7 Articles
Healthcare issues arose from population aging. Meanwhile, electrocardiogram (ECG) is a powerful measurement tool. The first\nstep of ECG is to detect QRS complexes. A state-of-the-art QRS detection algorithm was modified and implemented to an\napplication-specific integrated circuit (ASIC). By the dedicated architecture design, the novel ASIC is proposed with 0.68mm2\ncore area and 2.21 �µW power consumption. It is the smallest QRS detection ASIC based on 0.18 �µm technology. In addition, the\nsensitivity is 95.65% and the positive prediction of the ASIC is 99.36% based on the MIT/BIH arrhythmia database certification....
Synchronous early-completion-prediction adders (ECPAs) are used for high clock rate and high-precision DSP datapaths, as they allow a dominant amount of single-cycle operations even if the worst-case carry propagation delay is longer than the clock period. Previous works have also demonstrated ECPA advantages for average leakage reduction and NBTI effects reduction in nanoscale CMOS technologies. This paper illustrates a general systematic methodology to design ECPA units, targeting nanoscale CMOS technologies, which is not available in the current literature yet. The method is fully compatible with standard VLSI macrocell design tools and standard adder structures and includes automatic definition of critical test patterns for postlayout verification. A design example is included, reporting speed and power data superior to previous works....
The scan chain insertion problem is one of the mandatory logic insertion design tasks. The scanning of designs is a very efficient\r\nway of improving their testability. But it does impact size and performance, depending on the stitching ordering of the scan\r\nchain. In this paper, we propose a graph-based approach to a stitching algorithm for automatic and optimal scan chain insertion\r\nat the RTL. Our method is divided into two main steps. The first one builds graph models for inferring logical proximity\r\ninformation from the design, and then the second one uses classic approximation algorithms for the traveling salesman problem\r\nto determine the best scan-stitching ordering. We show how this algorithm allows the decrease of the cost of both scan analysis\r\nand implementation, by measuring total wirelength on placed and routed benchmark designs, both academic and industrial....
Power dissipation has been an inevitable problem of LCD systems for years. To ease the problem, many encoding methods have\r\nbeen developed, such as the methods of transition minimized differential signaling, the most popular one in use for DVI to date,\r\nchromatic encoding, and limited intraword transition. In this paper, the authors present the absolute difference and low-power\r\nencoding method for the serial transmission of LCD digital DVI display interface. In regard to the LCD digital display interface\r\nwith UMC 90nm technology, the proposed method minimizes the architectural complexity and reduces the power dissipation by\r\nabout 67% and 12%, respectively, compared with the transition minimized differential signaling and limited intraword transition.\r\nIn short, the proposed method is an efficient bus encoding method to largely decrease the dynamic and total power dissipation of\r\nthe LCD digital display interfaces....
This paper presents the comprehensive study and analysis of Golumb codes used for the test vector compression and Decompression in the field of VLSI testing. The Golumb codes are targeted to minimize the size of test data, which trim down the size of memory required in ATE. This paper also gives out an idea about the design of Golumb Encoder & Decoder using VHDL for the test vectors thus achieving a good height of compression ratio. The Modified Golumb coder eradicates the drawbacks of the simple Golumb Encoder and Decoder.In order to prove its legality, the developed algorithm is simulated using the Xilinx 9.2i and Quartus software....
In this paper, we present and compare efficient low-power hardware architectures for accelerating the Packet Data Convergence Protocol (PDCP) in LTE and LTE-Advanced mobile terminals. Specifically, our work proposes the design of two cores: a crypto engine for the Evolved Packet System Encryption Algorithm (128-EEA2) that is based on the AES cipher and a coprocessor for the Least Significant Bit (LSB) encoding mechanism of the Robust Header Compression (ROHC) algorithm. With respect to the former, first we propose a reference architecture, which reflects a basic implementation of the algorithm, then we identify area and power bottle-necks in the design and finally we introduce and compare several architectures targeting the most power-consuming operations. With respect to the LSB coprocessor, we propose a novel implementation based on a one-hot encoding, thereby reducing hardware�s logic switching rate. Architectural hardware analysis is performed using Faraday�s 90?nm standard-cell library. The obtained results, when compared against the reference architecture, show that these novel architectures achieve significant improvements, namely, 25% in area and 35% in power consumption for the 128-EEA2 crypto-core, and even more important reductions are seen for the LSB coprocessor, that is, 36% in area and 50% in power consumption....
The CANopen protocol is gaining great interest from the Industrial community for automation. In an industry it is very important to automate the fault tolerance methods for the tasks to be carried out without any interrupt. The CANopen protocol provides the gateway to implement such systems which will be self correcting. Thus without any human monitoring the fault in the system will be self rectified from the system. The paper provides idea of the intelligent fault tolerance system design using CANopen protocol. The simulations of various transmitter blocks are shown with the idea of implementation....
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