Current Issue : October - December Volume : 2013 Issue Number : 4 Articles : 9 Articles
The performance of Digital PLL is primarily dependent on the lock time, it is the time the PLL takes to adapt and settle after a sudden change of the input signal frequency. It is desired to design a fast locking DPLL. The high speed throughput applications needed for information technology demand that the lock time should be as small as possible. Fast locking is also of great importance for fast frequency hopping among data bursts in high-speed digital communications. The fast locking DPLL proposed in this paper contains two main stages of tunings the wide frequency range, as a coarse stage and fine stage. The DPLL design implemented on Advance Design System Tool in 0.18μm CMOS process using BSIM3 model and can operate from 200MHz to 1.8 GHz with 3.3V power supply. The main aim of the work is to enhance the performance of DPLL by reducing the lock time below 100 nsec for wider RF rage and to achieve a high degree of accuracy in the work. Thus, it can reduce the design complexity as well as locking time of the DPLL, making it very proper design for system-on-chip applications....
A prototype-based SoC performance estimation methodology was proposed for consumer electronics design. Traditionally,\r\nprototypes are usually used in system verification before SoC tapeout, which is without accurate SoC performance exploration and\r\nestimation.This paper attempted to carefully model the SoC prototype as a performance estimator and explore the environment of\r\nSoC performance.The prototype met the gate-level cycle-accurate requirement, which covered the effect of embedded processor,\r\non-chip bus structure, IP design, embedded OS, GUI systems, and application programs.The prototype configuration, chip postlayout\r\nsimulation result, and the measured parameters of SoC prototypes were merged to model a target SoC design. The system\r\nperformance was examined according to the proposed estimation models, the profiling result of the application programs ported\r\non prototypes, and the timing parameters from the post-layout simulation of the target SoC. The experimental result showed that\r\nthe proposed method was accompanied with only an average of 2.08% of error for an MPEG-4 decoder SoC at simple profile level\r\n2 specifications....
As conventional MOSFETs channel lengths are scaled down below 100 nm for improved performance and packing density, the gate oxide thickness is also scaled below 3 nm. Due to this aggressive scaling short channel effects (SCEs) like threshold voltage roll-off & gate leakage current play a major role in determining the performance of scaled devices. The double gate (DG) MOSFETs are electro-statically superior to a single gate (SG) MOSFET and allows for additional gate length scaling [1]. On the other hand, nanotechnology has achieved significant progress in recent years, fabricating a variety of nanometer scale devices, e.g., molecular diodes and Carbon Nanotube field effect transistors (CNFETs). This has provided new opportunities for VLSI circuits to achieve continuing cost minimization and performance improvement in a post-silicon-based-CMOS-technology era. Carbon Nanotube based FET devices are getting more and more importance today because of their high channel mobility, improved voltage characteristics & have been considered as a replacement for future semiconductor devices due to high mobility, low defect structure, and intrinsic nanometer scale of Carbon Nanotubes (CNTs) [8]. So by changing the material like polysilicon with Carbon Nanotube the short channel effect can be reduced. The attempt has been made to change the material exist in Silvaco''s TCAD library to Carbon Nanotube environment for model MOSFET-like DG CNFET device. This study present VI characteristic of DG CNFET to achieves its objectives [2]. Simulation work on DG CNFET is carried out to investigate the dependence of I-V characteristics on various polysilicon (as Carbon Nanotube channel) thickness, doping level on polysilicon (as Carbon Nanotube channel) and mobility defined on polysilicon to be Carbon Nanotube environment. Now by comparing the characteristics of DG MOSFET characteristics with DG CNFET characteristics...
Multiplication is frequently required in Digital Signal Processing (DSP). Parallel multipliers provide a high-speed method for multiplication, but require large area for VLSI implementations. In most signal processing applications, a rounded product is desired to avoid growth in word-size. Truncated multiplication provides an efficient method for reducing the power dissipation and area of rounded parallel multipliers in digital signal processing systems. With this technique, the partial parallel multipliers are rounded to a shorter word size and the least-significant columns of the multiplication matrix are not used and the carry generated by these is added in most significant columns. In this paper a Left-to-right (LR) parallel multipliers are designed with the truncated scheme. In this paper, we will design both array structure and tree structure with compressors for LR and Right-to-Left parallel multipliers and compared their results. Simulation results show that LR multiplier with truncated scheme consumes 25% to 30% less power than Right-to-left (RL) multiplier with truncated scheme...
The Ultrawideband (UWB) imaging technique for breast cancer detection is based on the fact that cancerous cells have different\r\ndielectric characteristics than healthy tissues.When a UWB pulse in the microwave range strikes a cancerous region, the reflected\r\nsignal is more intense than the backscatter originating from the surrounding fat tissue. A UWB imaging system consists of\r\ntransmitters, receivers, and antennas for the RF part, and of a digital back-end for processing the received signals. In this paper we\r\nfocus on the imaging unit, which elaborates the acquired data and produces 2D or 3D maps of reflected energies.We show that one\r\nof the processing tasks, Beamforming, is the most timing critical and cannot be executed in software by a standard microprocessor\r\nin a reasonable time.We thus propose a specialized hardware accelerator for it.We design the accelerator in VHDL and test it in an\r\nFPGA-based prototype. We also evaluate its performance when implemented on a CMOS 45 nm ASIC technology. The speed-up\r\nwith respect to a software implementation is on the order of tens to hundreds, depending on the degree of parallelism permitted\r\nby the target technology....
Multiple input multiple output-orthogonal frequency division multiplexing (MIMO-OFDM) with an electronically steerable\r\npassive array radiator (ESPAR) antenna receiver can improve the bit error rate performance and obtains additional diversity gain\r\nwithout increasing the number of Radio Frequency (RF) front-end circuits.However, due to the large size of the channel matrix, the\r\ncomputational cost required for the detection process using Vertical-Bell Laboratories Layered Space-Time (V-BLAST) detection\r\nis too high to be implemented. Using the minimum mean square error sparse-sorted QR decomposition (MMSE sparse-SQRD)\r\nalgorithm for the detection process the average computational cost can be considerably reduced but is still higher compared with a\r\nconventional MIMOOFDM system without ESPAR antenna receiver. In this paper, we propose to use a low complexity submatrix\r\ndividedMMSE sparse-SQRDalgorithmfor the detection process ofMIMOOFDMwith ESPARantenna receiver.Thecomputational\r\ncost analysis and simulation results show that on average the proposed scheme can further reduce the computational cost and\r\nachieve a complexity comparable to the conventional MIMO-OFDM detection schemes....
Power amplifiers are a key part of RF transmitters. Power amplifiers can be designed and fabricated using CMOS, BiCMOS, GaAs-HBT, GaN-HEMT technologies. The main performance parameters for the power amplifier are power gain, linearity, and efficiency. For a power amplifier there are two types of efficiencies known as drain efficiency and Power Added Efficiency. PAE is the most important factor for evaluation of the performance of the power amplifier. GaAs-HBT and GaN-HEMT technologies provide high output power but dissipate large amount of power and requires large chip area. CMOS power amplifiers dissipate less power as compared to other technologies due to its ability to operate at very low voltages and the total chip size is also very less. CMOS power amplifiers are also very cost effective as compared to other available technologies. Power amplifiers find themselves in many wireless applications such as WLAN, WiMAX, Bluetooth, etc. WLAN operates in RF bands of 2.4, 3.6 and 5 GHz. The RF band of 2.4 GHz is a free ISM band....
As per the International Technology Roadmap for Semiconductors (ITRS) each lower node is 0.7 times the previous technology making chip faster by 17% every year. Scaling down of CMOS technologies to 22nm has significant challenges in design. By reducing the dimensions many challenges like gate leakage, short channel effect (SCE), low voltage operation & delay comes into picture. Thus paper presents the past work done in design of nanoscale MOSFETs. The multi gate MOSFETs structure is considered as important candidates for CMOS scaling to reduce short channel effect. Gate All Around (GAA) & Double Gate (DG) are another design used to reduce SCE & suitable for low voltage operation. Use of Silicon on Insulator (SOI) for the thin short channel, Lower parasitic capacitance, Resistance to Latchup & has 10-20% higher switching speed. This paper shows the various challenges in design of MOSFET & various methods or techniques for increasing the performance of MOSFET at lower node...
Digital wave generators are used in plenty of applications. Wireless and mobile systems are among the fastest growing application areas in which digital modalities of sine and cosine waves have received special attention. CORDIC is an arithmetic algorithm widely used in the computing of elementary functions. CORDIC is an iterative algorithm for the calculation of the trigonometric functions using only add and shift operations. This paper presents a pipelined CORDIC architecture is used for designing a flexible and scalable digital sine and cosine waves generator. An FPGA-Based architecture is presented and the design has been implemented on a Xilinx using VHDL . Synthesis and simulation results are shown and discussed....
Loading....