Inventi Impact - Reconfigurable Computing
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Journal Scope:
‘Inventi Rapid/Impact: Reconfigurable Computing’ is a peer reviewed journal providing publishing space for the advancements taking place in the theory and practice of reconfigurable computing. The journal accepts research and review articles from academicians as well as practicing professionals.
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DESIGN AND IMPLEMENTATION OF RECONFIGURABLE HETEROGENEOUS ARCHITECTURE USING SOFT CORE PROCESSOR AND DSP ACCELERATOR
In the last few years speed of processor increased every six month to one year. We have requirement of parallel processing for some scientific research work such as bio-medical research, earthquake analysis and for high definition video. For parallel processing require multi-core architecture. With Multi-core architecture we can improve system performance up to some limitation because we can’t r...
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DISTANCE-RANKED FAULT IDENTIFICATION OF RECONFIGURABLE HARDWARE BITSTREAMS VIA FUNCTIONAL INPUT
Distance-Ranked Fault Identification (DRFI) is a dynamic reconfiguration technique which employs runtime inputs to conduct online functional testing of fielded FPGA logic and interconnect resources without test vectors. At design time, a diverse set of functionally identical bitstream configurations are created which utilize alternate hardware resources in the FPGA fabric. An ordering is imposed o...
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USING STATISTICAL ASSERTIONS TO GUIDE SELF-ADAPTIVE SYSTEMS
Self-adaptive systems need to monitor themselves, to check their internal behaviour and design assumptions about runtime inputs and conditions. This kind of monitoring for self-adaptive systems can include collecting statistics about such systems themselves which can be computationally intensive (for detailed statistics) and hence time consuming, with possible negative impact on selfadaptive respo...
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A TOP-DOWN OPTIMIZATION METHODOLOGY FOR MUTUALLY EXCLUSIVE APPLICATIONS
Proliferation ofmutually exclusive applications on circuits and the higher cost of silicon make the resource sharing more and more important.Thestate-of-the-art synthesis toolsmay often be unsatisfactory. Their efficiencymay depend on the hardware description style.Nevertheless, today, different applications in a circuit can be developed by different developers. This paper proposes an efficient me...
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HARDWARE-EFFICIENT DESIGN OF REAL-TIME PROFILE SHAPE MATCHING STEREO VISION ALGORITHM ON FPGA
A variety of platforms, such as micro-unmanned vehicles, are limited in the amount of computational hardware they can support due to weight and power constraints. An efficient stereo vision algorithm implemented on an FPGA would be able to minimize payload and power consumption in microunmanned vehicles, while providing 3D information and still leaving computational resources available for other p...
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IP-ENABLED C/C++ BASED HIGH LEVEL SYNTHESIS: A STEP TOWARDS BETTER DESIGNER PRODUCTIVITY AND DESIGN PERFORMANCE
Intellectual property (IP) core based design is an emerging design methodology to deal with increasing chip design complexity. C/C++ based high level synthesis (HLS) is also gaining traction as a design methodology to deal with increasing design complexity. In the work presented here, we present a design methodology that combines these two individual methodologies and is therefore more powerful...
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