Frequency: Quarterly E- ISSN: 2277-6338 P- ISSN: Awaited Abstracted/ Indexed in: CNKI Scholar (China National Knowledge Infrastructure), Ulrichâ??s International Periodical Directory, Google Scholar, SCIRUS, getCITED, Genamics JournalSeek
â??Inventi Rapid/Impact: Reconfigurable Computingâ?? is a peer reviewed journal providing publishing space for the advancements taking place in the theory and practice of reconfigurable computing. The journal accepts research and review articles from academicians as well as practicing professionals.
This paper outlines a new polarization reconfigurable EBG (Electromagnetic Band\nGap) antenna in the 60 GHz millimeter waves band. The proposed hybrid antenna is\ncomposed of a multilayer pyramidal DRA (Dielectric Resonator Antenna) exciting\nsource covered with a FSS (frequency Selective Surface) superstrate. The device can\nswitch between circular and linear polarization by a simple 45Ã?Å¡ mechanical rotation\nof the pyramidal DRA. This structure has the advantage that it maintained stable\nbandwidth, gain, efficiency and radiation properties when switching between the two\nconfigurations of circular and linear polarization....
We propose a fast data relay (FDR) mechanism to enhance existing CGRA (coarse-grained reconfigurable architecture). FDR\r\ncan not only provide multicycle data transmission in concurrent with computations but also convert resource-demanding\r\ninter-processing-element global data accesses into local data accesses to avoid communication congestion. We also propose\r\nthe supporting compiler techniques that can efficiently utilize the FDR feature to achieve higher performance for a variety of\r\napplications. Our results on FDR-based CGRA are compared with two other works in this field: ADRES and RCP. Experimental\r\nresults for various multimedia applications show that FDR combined with the new compiler deliver up to 29% and 21% higher\r\nperformance than ADRES and RCP, respectively....
The main topic of this paper is low-cost public key cryptography in wireless sensor nodes. Security in embedded systems, for\nexample, in sensor nodes based on field programmable gate array (FPGA), demands low cost but still efficient solutions. Sensor\nnodes are key elements in the Internet of Things paradigm, and their security is a crucial requirement for critical applications in\nsectors such as military, health, and industry. To address these security requirements under the restrictions imposed by the\navailable computing resources of sensor nodes, this paper presents a low-area FPGA-prototyped hardware accelerator for scalar\nmultiplication, the most costly operation in elliptic curve cryptography (ECC). This cryptoengine is provided as an enabler of\nrobust cryptography for security services in the IoT, such as confidentiality and authentication. The compact property in the\nproposed hardware design is achieved by implementing a novel digit-by-digit computing approach applied at the finite field and\ncurve level algorithms, in addition to hardware reusing,.............................
Many artificial intelligence applications often require a huge amount of computing\nresources. As a result, cloud computing adoption rates are increasing in the artificial intelligence\nfield. To support the demand for artificial intelligence applications and guarantee the service level\nagreement, cloud computing should provide not only computing resources but also fundamental\nmechanisms for efficient computing. In this regard, a snapshot protocol has been used to create a\nconsistent snapshot of the global state in cloud computing environments. However, the existing\nsnapshot protocols are not optimized in the context of artificial intelligence applications, where\nlarge-scale iterative computation is the norm. In this paper, we present a distributed snapshot protocol\nfor efficient artificial intelligence computation in cloud computing environments. The proposed\nsnapshot protocol is based on a distributed algorithm to run interconnected multiple nodes in a\nscalable fashion. Our snapshot protocol is able to deal with artificial intelligence applications, in which\na large number of computing nodes are running. We reveal that our distributed snapshot protocol\nguarantees the correctness, safety, and liveness conditions....
Because wireless sensor networks (WSNs) are complex and difficult to deploy and manage, appropriate structures are required to\nmake these networks more flexible. In this paper, a reconfigurable testbed is presented, which supports dynamic protocol switching\nby creating a novel architecture and experiments with several different protocols. The separation of the control and data planes\nin this testbed means that routing configuration and data transmission are independent. A programmable flow table provides the\ntestbed with the ability to switch protocols dynamically.We experiment on various aspects of the testbed to analyze its functionality\nand performance. The results demonstrate that sensors in the testbed are easy to manage and can support multiple protocols. We\nthen raise some important issues that should be investigated in future work concerning the testbed....
Malicious software has become a major threat to computer users on the Internet today. Security researchers need to gather and\r\nanalyze large sample sets to develop effective countermeasures. The setting of honeypots, which emulate vulnerable applications,\r\nis one method to collect attack code. We have proposed a dedicated hardware architecture for honeypots which allows both highspeed\r\noperation at 10 Gb/s and beyond and offers a high resilience against attacks on the honeypot infrastructure itself. In this\r\nwork, we refine the base NetStage architecture for better management and scalability. Using dynamic partial reconfiguration, we\r\ncan now update the functionality of the honeypot during operation. To allow the operation of a larger number of vulnerability\r\nemulation handlers, the initial single-device architecture is extended to scalable multichip systems. We describe the technical\r\naspects of these modifications and show results evaluating an implementation on a current quad-FPGA reconfigurable computing\r\nplatform....
An FPGA-based Linux test-bed was constructed for the purpose of measuring its sensitivity to single-event upsets. The test-bed\r\nconsists of two ML410 Xilinx development boards connected using a 124-pin custom connector board. The Design Under Test\r\n(DUT) consists of the ââ?¬Å?hard coreââ?¬Â PowerPC, running the Linux OS and several peripherals implemented in ââ?¬Å?softââ?¬Â (programmable)\r\nlogic. Faults were injected via the Internal Configuration Access Port (ICAP). The experiments performed here demonstrate that\r\nthe Linux-based system was sensitive to 199,584 or about 1.4 percent of all tested bits. Each sensitive bit in the bit-stream is\r\nmapped to the resource and user-module to which it configures. A density metric for comparing the reliability of modules within\r\nthe system is presented. Using this density metric, we found that the most sensitive user module in the design was the PowerPCââ?¬â?¢s\r\ndirect connections to the DDR2 memory controller....
Mathematical morphology supplies powerful tools for low-level image analysis. Many applications in computer vision require\r\ndedicated hardware for real-time execution. The design of morphological operators for a given application is not a trivial one.\r\nGenetic programming is a branch of evolutionary computing, and it is consolidating as a promising method for applications\r\nof digital image processing. The main objective of genetic programming is to discover how computers can learn to solve\r\nproblems without being programmed for that. In this paper, the development of an original reconfigurable architecture using\r\nlogical, arithmetic, and morphological instructions generated automatically by a genetic programming approach is presented.\r\nThe developed architecture is based on FPGAs and has among the possible applications, automatic image filtering, pattern\r\nrecognition and emulation of unknown filter. Binary, gray, and color image practical applications using the developed architecture\r\nare presented and the results are compared with similar techniques found in the literature....
Nonuniform random numbers are key for many technical applications, and designing efficient hardware implementations of nonuniform\r\nrandom number generators is a very active research field. However, most state-of-the-art architectures are either tailored\r\nto specific distributions or use up a lot of hardware resources. At ReConFig 2010, we have presented a new design that saves up\r\nto 48% of area compared to state-of-the-art inversion-based implementation, usable for arbitrary distributions and precision. In\r\nthis paper, we introduce a more flexible version together with a refined segmentation scheme that allows to further reduce the\r\napproximation error significantly. We provide a free software tool allowing users to implement their own distributions easily, and\r\nwe have tested our random number generator thoroughly by statistic analysis and two application tests....
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