Frequency: Quarterly E- ISSN: 2277-6338 P- ISSN: Awaited Abstracted/ Indexed in: Ulrich's International Periodical Directory, Google Scholar, SCIRUS, getCITED, Genamics JournalSeek, EBSCO Information Services
"Inventi Impact: Reconfigurable Computing" is a peer reviewed journal providing publishing space for the advancements taking place in the theory and practice of reconfigurable computing. The journal accepts research and review articles from academicians as well as practicing professionals.
This paper outlines a new polarization reconfigurable EBG (Electromagnetic Band\nGap) antenna in the 60 GHz millimeter waves band. The proposed hybrid antenna is\ncomposed of a multilayer pyramidal DRA (Dielectric Resonator Antenna) exciting\nsource covered with a FSS (frequency Selective Surface) superstrate. The device can\nswitch between circular and linear polarization by a simple 45Ã?Å¡ mechanical rotation\nof the pyramidal DRA. This structure has the advantage that it maintained stable\nbandwidth, gain, efficiency and radiation properties when switching between the two\nconfigurations of circular and linear polarization....
Fractional-order Butterworth filters of order 1 + α (0 <α <1) can be implemented by a unified structure, using the method presented in this paper. The main offered benefit is that the cutoff frequencies of the filters are fully controllable using a very simple method and, also, various types of filters (e.g., low-pass, high-pass, band-pass, and band-stop) could be realized. Thanks to the employment of a Field Programmable Analog Array device, the implementation of the introduced method is fully reconfigurable, in the sense that various types of filter functions as well as their order are both programmable....
We propose a fast data relay (FDR) mechanism to enhance existing CGRA (coarse-grained reconfigurable architecture). FDR\r\ncan not only provide multicycle data transmission in concurrent with computations but also convert resource-demanding\r\ninter-processing-element global data accesses into local data accesses to avoid communication congestion. We also propose\r\nthe supporting compiler techniques that can efficiently utilize the FDR feature to achieve higher performance for a variety of\r\napplications. Our results on FDR-based CGRA are compared with two other works in this field: ADRES and RCP. Experimental\r\nresults for various multimedia applications show that FDR combined with the new compiler deliver up to 29% and 21% higher\r\nperformance than ADRES and RCP, respectively....
The main topic of this paper is low-cost public key cryptography in wireless sensor nodes. Security in embedded systems, for example, in sensor nodes based on field programmable gate array (FPGA), demands low cost but still efficient solutions. Sensor nodes are key elements in the Internet of Things paradigm, and their security is a crucial requirement for critical applications in sectors such as military, health, and industry. To address these security requirements under the restrictions imposed by the available computing resources of sensor nodes, this paper presents a low-area FPGA-prototyped hardware accelerator for scalar multiplication, the most costly operation in elliptic curve cryptography (ECC). This cryptoengine is provided as an enabler of robust cryptography for security services in the IoT, such as confidentiality and authentication. The compact property in the proposed hardware design is achieved by implementing a novel digit-by-digit computing approach applied at the finite field and curve level algorithms, in addition to hardware reusing, the use of embedded memory blocks in modern FPGAs, and a simpler control logic. Our hardware design targets elliptic curves defined over binary fields generated by trinomials, uses fewer area resources than other FPGA approaches, and is faster than software counterparts. Our ECC hardware accelerator was validated under a hardware/software codesign of the Diffie-Hellman key exchange protocol (ECDH) deployed in the IoT MicroZed FPGA board. For a scalar multiplication in the sect233 curve, our design requires 1170 FPGA slices and completes the computation in 128820 clock cycles (at 135.31 MHz), with an efficiency of 0.209 kbps/slice. In the codesign, the ECDH protocol is executed in 4.1 ms, 17 times faster than a MIRACL software implementation running on the embedded processor Cortex A9 in the MicroZed. The FPGA-based accelerator for binary ECC presented in this work is the one with the least amount of hardware resources compared to other FPGA designs in the literature....
A real-time streaming feedforward active-noise-cancellation (ANC) system for an in-ear headphone was demonstrated in a real application scenario, by implementing a 10-layer dilated convolutional-neural-network (CNN) on a field programmable gate array (FPGA). A 16 × 16 systolic array was used in the FPGA, to speed up the model computation. The system latency was 170.6 μs, at the system clock frequency of 120 MHz. The CNN model used 3232 parameters. Due to the large input receptive field, of 327 ms, this work achieved total power reduction, of 14.8 dB and 14.3 dB at the noise incident direction of 0◦ and 90◦, respectively, and the noise attenuation bandwidth was 2000 Hz at both angles; all results were superior to those of the conventional FxLMS algorithm....
Many artificial intelligence applications often require a huge amount of computing\nresources. As a result, cloud computing adoption rates are increasing in the artificial intelligence\nfield. To support the demand for artificial intelligence applications and guarantee the service level\nagreement, cloud computing should provide not only computing resources but also fundamental\nmechanisms for efficient computing. In this regard, a snapshot protocol has been used to create a\nconsistent snapshot of the global state in cloud computing environments. However, the existing\nsnapshot protocols are not optimized in the context of artificial intelligence applications, where\nlarge-scale iterative computation is the norm. In this paper, we present a distributed snapshot protocol\nfor efficient artificial intelligence computation in cloud computing environments. The proposed\nsnapshot protocol is based on a distributed algorithm to run interconnected multiple nodes in a\nscalable fashion. Our snapshot protocol is able to deal with artificial intelligence applications, in which\na large number of computing nodes are running. We reveal that our distributed snapshot protocol\nguarantees the correctness, safety, and liveness conditions....
Because wireless sensor networks (WSNs) are complex and difficult to deploy and manage, appropriate structures are required to\nmake these networks more flexible. In this paper, a reconfigurable testbed is presented, which supports dynamic protocol switching\nby creating a novel architecture and experiments with several different protocols. The separation of the control and data planes\nin this testbed means that routing configuration and data transmission are independent. A programmable flow table provides the\ntestbed with the ability to switch protocols dynamically.We experiment on various aspects of the testbed to analyze its functionality\nand performance. The results demonstrate that sensors in the testbed are easy to manage and can support multiple protocols. We\nthen raise some important issues that should be investigated in future work concerning the testbed....
Malicious software has become a major threat to computer users on the Internet today. Security researchers need to gather and\r\nanalyze large sample sets to develop effective countermeasures. The setting of honeypots, which emulate vulnerable applications,\r\nis one method to collect attack code. We have proposed a dedicated hardware architecture for honeypots which allows both highspeed\r\noperation at 10 Gb/s and beyond and offers a high resilience against attacks on the honeypot infrastructure itself. In this\r\nwork, we refine the base NetStage architecture for better management and scalability. Using dynamic partial reconfiguration, we\r\ncan now update the functionality of the honeypot during operation. To allow the operation of a larger number of vulnerability\r\nemulation handlers, the initial single-device architecture is extended to scalable multichip systems. We describe the technical\r\naspects of these modifications and show results evaluating an implementation on a current quad-FPGA reconfigurable computing\r\nplatform....
An FPGA-based Linux test-bed was constructed for the purpose of measuring its sensitivity to single-event upsets. The test-bed\r\nconsists of two ML410 Xilinx development boards connected using a 124-pin custom connector board. The Design Under Test\r\n(DUT) consists of the ââ?¬Å?hard coreââ?¬Â PowerPC, running the Linux OS and several peripherals implemented in ââ?¬Å?softââ?¬Â (programmable)\r\nlogic. Faults were injected via the Internal Configuration Access Port (ICAP). The experiments performed here demonstrate that\r\nthe Linux-based system was sensitive to 199,584 or about 1.4 percent of all tested bits. Each sensitive bit in the bit-stream is\r\nmapped to the resource and user-module to which it configures. A density metric for comparing the reliability of modules within\r\nthe system is presented. Using this density metric, we found that the most sensitive user module in the design was the PowerPCââ?¬â?¢s\r\ndirect connections to the DDR2 memory controller....
In this paper, a low-profile, compact size, inexpensive, and easily integrable frequency reconfigurable antenna system is proposed. The proposed antenna consists of an inverted-F shape antenna, capacitors, and switching PIN diodes. The designed antenna element is fabricated on easy available and less expensive FR-4 substrate (εr 4.4, tan δ 0.02). The switching diodes are incorporated within the radiating structure of the antenna design, and by changing the different states of PIN diodes, frequency reconfigurable response is achieved. While adjusting the different states of the diodes, the antenna resonates between 0.841 GHz and 2.12 GHz and covers six different frequency bands. The proposed system has compact size of 44 × 14 × 3.2mm3. The gain of the antenna is between 1.89 and 2.12 dBi. The measurement results shows the good agreement with simulated results for different key performance parameters. Additionally, the proposed antenna shows omni-directional far-field characteristics for various different frequencies....
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