Frequency: Quarterly E- ISSN: 2277-2294 P- ISSN: Awaited Abstracted/ Indexed in: Ulrich's International Periodical Directory, Google Scholar, SCIRUS, Genamics JournalSeek, EBSCO Information Services
Quarterly published "Inventi Impact: Electronic Components" publishes high quality unpublished as well as high impact pre-published research and reviews catering to the needs of researchers and professional engineers. The journal deals with the theory and experimentation aspects of all kinds of electronic components and includes topics such as electron tubes, transistors, integrated circuits, semiconductor materials, thick-film materials, resistors, capacitors and solid-state memories.
This is Part II of a two-part paper that explores the 28-nm UTBB FD-SOI\nCMOS and the 22-nm Tri-Gate FinFET technology as the better alternatives\nto bulk transistors especially when the transistor�s architecture is going fully\ndepleted and its size is becoming much smaller, 28-nm and above. Reliability\ntests of those alternatives are first discussed. Then, a comparison is made between\nthe two alternative transistors comparing their physical properties, electrical\nproperties, and their preferences in different applications....
A split‐gate metal–oxide–semiconductor field‐effect transistor (SG‐DMOSFET) is a wellknown structure used for reducing the gate–drain capacitance (CGD) to improve switching characteristics. However, SG‐DMOSFETs have problems such as the degradation of static characteristics and a high gate‐oxide electric field....................
A high-speed, high-depth pre-interleaver in the proposed symbol pre-interleaving Bit MUX (PBM) was implemented to mitigate decision feedback equalizer (DFE) error propagation in a 400 G Ethernet Serializer–Deserializer (SerDes) interface. Based on the SerDes interface link architecture with 5-tap DFE, the performance of the PBM under DFE error propagation was simulated theoretically, which could obtain an interleaving gain of 0.35 dB. In the pre-interleaver, in order to significantly increase the transmission rate while keeping the larger interleaving depth, characteristic polynomial parallelization with the logic expansion method and register-based memory with interleaving technology were adopted. Finally, the pre-interleaver was fabricated with 65 nm CMOS technology, with a total area of 0.615 mm2, including the I/O pad. The measurement results show that the horizontal opening degree of the output signal can reach 0.925 UI at the data rate of 41.6 Gb/s. The total power consumption is 38.52 mW at the supply voltage of 1.2 V and frequency of 1.3 GHz....
In this review paper, an overview of the application of n‐type 4H‐SiC Schottky barrier diodes (SBDs) as radiation detectors is given. We have chosen 4H‐SiC SBDs among other semiconductor devices such as PiN diodes or metal‐oxide‐semiconductor (MOS) structures, as significant progress has been achieved in radiation detection applications of SBDs in the last decade. Here, we present the recent advances at all key stages in the application of 4H‐SiC SBDs as radiation detectors, namely: SBDs fabrication, electrical characterization of SBDs, and their radiation response. The main achievements are highlighted, and the main challenges are discussed....
LEDs are highly energy efficient and have substantially longer lifetimes compared to other\nexisting lighting technologies. In order to facilitate the new generation of LED devices, approaches to\nimprove power efficiency with increased integration level for lighting device should be analysed.\nThis paper proposes a fully on-chip integrated LED driver design implemented using heterogeneous\nintegration of gallium nitride (GaN) devices atop BCD circuits. The performance of the proposed\ndesign is then compared with the conventional fully on-board integration of power devices with the\nLED driver integrated circuit (IC). The experimental results confirm that the fully on-chip integrated\nLED driver achieves a consistently higher power efficiency value compared with the fully on-board\ndesign within the input voltage range of 4.5â??5.5 V. The maximal percentage improvement in the\nefficiency of the on-chip solution compared with the on-board solution is 18%....
A wideband (0.8ââ?¬â??6GHz) receiver front-end (RFE) utilizing a shunt resistive feedback low-noise amplifier (LNA) and a micromixer\r\nis realized in 90nm CMOS technology for software-defined radio (SDR) applications.With the shunt resistive feedback and series\r\ninductive peaking, the proposed LNA is able to achieve a wideband frequency response in input matching, power gain and noise\r\nfigure (NF). A micromixer down converts the radio signal and performs single-to-differential transition. Measurements show the\r\nconversion gain higher than 17 dB and input matching (S11) better than -7.3 dB from 0.8 to 6GHz. The IIP3 ranges from -7 to\r\n-10 dBm, and the NF from 4.5 to 5.9 dB. This wideband receiver occupies 0.48mm2 and consumes 13mW....
Apower efficient circuit topology is proposed to implement a low-voltageCMOS 2-input pass-transistorXOR gate. This design aims\r\nto minimize power dissipation and reduce transistor count while at the same time reducing the propagation delay. The XOR gate\r\nutilizes six transistors to achieve a compact circuit design and was fabricated using the 130 nmIBMCMOS process.Theperformance\r\nof the XOR circuit was validated against other XOR gate designs through simulations using the same 130 nm CMOS process. The\r\narea of the core circuit is only about 56 sq �· ??m with 1.5659 ns propagation delay and 0.2312 nW power dissipation at 0.8V supply\r\nvoltage. The proposed six-transistor implementation thus compares favorably with other existing XOR gate designs....
This paper describes a fourth-order cascade-of-integrators with feedforward (CIFF)\nsingle-bit discrete-time (DT) switched-capacitor (SC) delta-sigma modulator (DSM) for high-resolution\napplications. This DSM is suitable for high-resolution applications at low frequency using a high-order\nmodulator structure. The proposed operational transconductance amplifier (OTA), used a feedforward\namplifier scheme that provided a high-power efficiency, a wider bandwidth, and a higher DC gain\ncompared to recent designs. A chopper-stabilization technique was applied to the first integrator to\nremove the 1/f noise from the transistor, which is inversely proportional to the frequency. The designed\nDSM was implemented using 0.35 micromcomplementary metal oxide semiconductor (CMOS) technology.\nThe oversampling ratio (OSR) was 128, and the sampling frequency was 128 kHz. At a 500 Hz\nbandwidth, the signal-to-noise ratio (SNR) was 100.3 dB, the signal-to-noise distortion ratio (SNDR)\nwas 98.5 dB, and the dynamic range (DR) was 103 dB. The measured total power dissipation was\n99 microW from a 3.3 V supply voltage....
This paper reports a 12GHz rotary travelling wave (RTW) voltage controlled oscillator designed in a 130nm CMOS technology.\r\nThe phase noise and power consumption performances were compared with the literature and with telecommunication standards\r\nfor broadcast satellite applications. The RTW VCO exhibits a -106 dBc/Hz at 1MHz and a 30mW power consumption with a\r\nsensibility of 400 MHz/V. Finally, requirements are given for a PLL implementation of the RTW VCO and simulated results are\r\npresented....
In this paper, a novel 12-bit current-steering binary-weighted digital-to-analog converter (DAC) based on\nnanoampere bits is designed and modified for high-definition television (HDTV) applications. As a part of a\nwidely used consumer appliance, it is aimed to be such designed to consume power as low as possible.\nHence, as a distinguished idea, prime concentration is focused on the reduction of the currents providing the\nbits of the proposed DAC. To do this, current mirrors operating in the weak inversion region are arranged to\nestablish the least significant bit (LSB) current as low as 10 nA while the power supply is also reduced to 1 V,\nresulting to an ultralow power of 52.9 �µW. Many other powerful ideas are then deliberately combined to\nmaintain both high speed and very low glitches required for HDTV application despite those ultralow currents\nand power. The result is a speed of 100 MS/s, an ultralow glitch of ?10.91 fAs, |INL| = 0.988 LSB, |DNL|\n= 0.99 LSB, and a spurious-free dynamic range of ?73 dB. These results caused the proposed DAC to execute\na distinguished overall performance (defined as figure of merit) greatly better than some other advanced\nones by outstanding ratios of 77 to 277,185. Hspice simulations with the SMIC 0.18-�µm complementary\nmetal-oxide semiconductor technology have been used to validate the proposed circuit. Performance\nevaluation of the proposed DAC versus Monte Carlo simulations and also a wide range of temperature\nvariations proved both its well mismatch insensitivity and thermal stability....
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