Frequency: Quarterly E- ISSN: 2277-2618 P- ISSN: 2349-3461 Abstracted/ Indexed in: Ulrich's International Periodical Directory, Google Scholar, SCIRUS, Genamics JournalSeek, EBSCO Information Services
Quarterly published "Inventi Impact: Embedded Systems" publishes high quality unpublished as well as high impact pre-published research and reviews catering to the needs of researchers and professional engineers dealing with the theory and practice of embedded systems, particularly the ones used in designing homogeneous as well as heterogeneous embedded systems combining data and control driven behaviors.
Plastic pollution has a negative influence on biodiversity especially in aquatic ecosystems, and it has been labelled as one of the greatest dangers to biota. This paper proposes a Convolutional Neural Networks (CNN) based plastic detection model for the embedded platform to identify different shapes of underwater plastics such as bags, bottles, containers, cups, nets, pipes, ropes, snack wrappers and tarps. The model is optimized for Raspberry Pi using OpenVINO framework, with the intention to produce a cost-effective edge system for a Remote Operating Vehicle (ROV) system. The development of the model utilizes a pre-trained object detection model from YOLOv5 and the TrashCan 1.0 dataset, for training and testing. The final model exhibits a good performance, achieving more than 85% accuracy in the overall prediction, which highlights the model's accuracy and reliability in detecting and classifying underwater plastic shapes. Results from this work highlight the potential of the deep learning (DL) real-time embedded processing at the edge rather by a separate computer on land, using a cost-effective embedded platform....
Tuning cache hierarchies in platforms for embedded systems can significantly reduce energy consumption. In this paper we combined two optimization methods for tuning both instruction and data cache configurations in a two-level memory hierarchy, where both levels have separate instruction and data caches. This kind of hierarchy allows us to evaluate instruction and data caches branches separately, although previous approaches have applied the same method for both branches of the hierarchy. This work evaluates several methods intended for two-level hierarchies, and the results showed that when we combine different methods for each branch of the hierarchy, results can be improved. Experiments based on simulations were performed for 12 applications from the Mibench suite benchmark and the combined method achieved better efficiency in 60% of the evaluated cases compared with existing heuristics. The proposed solution is only 11% less economic in terms of energy consumption than optimal values and required, on average, 42 simulations to conclude optimization mechanism, representing only 9% of the design space....
The use of Hardware-in-the-Loop (HIL) systems implemented in Field Programmable\nGate Arrays (FPGAs) is constantly increasing because of its advantages compared to traditional\nsimulation techniques. This increase in usage has caused new challenges related to the improvement\nof their performance and features like the number of output channels, while the price of HIL systems\nis diminishing. At present, the use of low-speed Digital-to-Analog Converters (DACs) is starting to\nbe a commercial possibility because of two reasons. One is their lower price and the other is their\nlower pin count, which determines the number and price of the FPGAs that are necessary to handle\nthose DACs. This paper compares four filtering approaches for providing suitable data to low-speed\nDACs, which help to filter high-speed input signals, discarding the need of using expensive highspeed\nDACS, and therefore decreasing the total cost of HIL implementations. Results show that the\nselection of the appropriate filter should be based on the type of the input waveform and the relative\nimportance of the dynamics versus the area....
Topological indices are atomic auxiliary descriptors which computationally and hypothetically portray the natures of the basic availability of nanomaterials and chemical mixes, and henceforth, they give faster techniques to look at their exercises and properties. Anomaly indices are for the most part used to describe the topological structures of unpredictable graphs. Graph anomaly examines are helpful not only for quantitative structure-activity relationship (QSAR) and also quantitative structureproperty relationship (QSPR) but also for foreseeing their different physical and compound properties, including poisonousness, obstruction, softening and breaking points, the enthalpy of vanishing, and entropy. In this article, we discuss the irregularities of benzene ring and its line graph and compare them by its irregularity indices. We present graphical comparison by using Mathematica.......
Programmable logic controllers (PLCs) are complex embedded systems that are widely used in industry. This paper presents a\ncomponent-based modeling and validation method for PLC systems using the behavior-interaction-priority (BIP) framework.We\ndesigned a general system architecture and a component library for a type of device control system. The control software and\nhardware of the environment were all modeled as BIP components. System requirements were formalized as monitors. Simulation\nwas carried out to validate the systemmodel.Arealistic example fromindustry of the gates control system was employed to illustrate\nour strategies. We found a couple of design errors during the simulation, which helped us to improve the dependability of the\noriginal systems. The results of experiment demonstrated the effectiveness of our approach....
In recent years, the use of multiprocessor systems has become increasingly common. Even in the embedded domain,\nthe development of platforms based on multiprocessor systems or the porting of legacy single-core applications are\nfrequent needs. However, such designs are often complicated, as embedded systems are characterized by numerous\nnon-functional requirements and a tight hardware/software integration. This work proposes a methodology for the\ndevelopment and validation of an embedded multiprocessor system. Specifically, the proposed method assumes the\nuse of a portable, open source API to support the parallelization and the possibility of prototyping the system on a\nfield-programmable gate array. On this basis, the proposed flow allows an early exploration of the hardware\nconfiguration space, a preliminary estimate of performance, and the rapid development of a system able to satisfy the\ndesign specifications. An accurate assessment of the actual performance of the system is then enforced by the use of\nan hardware-based profiling subsystem. The proposed design flow is described, and a version specifically designed for\nLEON3 processor is presented and validated. The application of the proposed methodology in a real case of industrial\nstudy is then presented and analyzed....
With the widespread application of WIFI networks and embedded system\ntechnology, the device monitoring system based on Embedded System and\nwireless network came into being. In this paper, we introduce a device monitoring\nsystem based on ARM upper computer and WIFI transmission, and\nwe tested this system on workshop equipment. The hardware adopts ARM\nCortex-A8 processor architecture of TI company as the main control chip,\nusing IAC-335X-Kit development board for system design, external USB\ncamera module and WIFI wireless module for video capture and data transmission.\nThe software is based on embedded Linux as the platform. The system\nwill collect production data accurately and objectively, and the statistical\nanalysis. At the same time, the system uses QT to develop the upper computer\nsoftware GUI interface. Compared with the traditional system based on the\nwired network, our design is more convenient and flexible, which reduces the\nimplementation restriction and maintenance cost of traditional network\ncabling....
The capability to either minimize energy consumption in battery-operated devices, or to adequately exploit energy\nharvesting from various ambient sources, is central to the development and engineering of energy-neutral wireless\nsensor networks. However, the design of effective networked embedded systems targeting unlimited lifetime poses\nseveral challenges at different architectural levels. In particular, the heterogeneity, the variability, and the\nunpredictability of many energy sources, combined to changes in energy required by powered devices, make it\ndifficult to obtain reproducible testing conditions, thus prompting the need of novel solutions addressing these\nissues. This paper introduces a novel embedded hardware-software solution aimed at emulating a wide spectrum of\nenergy sources usually exploited to power sensor networks motes. The proposed system consists of a modular\narchitecture featuring small factor form, low power requirements, and limited cost. An extensive experimental\ncharacterization confirms the validity of the embedded emulator in terms of flexibility, accuracy, and latency while a\ncase study about the emulation of a lithium battery shows that the hardware-software platform does not introduce\nany measurable reduction of the accuracy of the model. The presented solution represents therefore a convenient\nsolution for testing large-scale testbeds under realistic energy supply scenarios for wireless sensor networks....
The development of modern networking requires that high-performance network\nprocessors be designed quickly and efficiently to support new protocols. As a very important\npart of the processor, the parser parses the headers of the packetsâ??this is the precondition for\nfurther processing and finally forwarding these packets. This paper presents a framework designed\nto transform P4 programs to VHDL and to generate parsers on Field Programmable Gate Arrays\n(FPGAs). The framework includes a pipeline-based hardware architecture and a back-end compiler.\nThe hardware architecture comprises many components with varying functionality, each of which\nhas its own optimized VHDL template. By using the output of a standard frontend P4 compiler,\nour proposed compiler extracts the parameters and relationships from within the used components,\nwhich can then be mapped to corresponding templates by configuring, optimizing, and instantiating\nthem. Finally, these templates are connected to output VHDL code. When a prototype of this\nframework is implemented and evaluated, the results demonstrate that the throughputs of the\ngenerated parsers achieve nearly 320 Gbps at a clock rate of around 300 MHz. Compared with\nstate-of-the-art solutions, our proposed parsers achieve an average of twice the throughput when\nsimilar amounts of resources are being used....
Embedded systems designers need to verify their design choices to find the proper platform and software that satisfy a given set of\r\nrequirements. In this context, it is essential to adopt formal-based techniques to evaluate the impact of design choices on system\r\nrequirements. To be useful, such techniques must produce accurate results with minimal computation time. This paper proposes\r\nan approach based on Coloured Petri Nets for evaluating embedded systems performance and energy consumption. In particular,\r\nthis work presents a method for specifying and evaluating the workload and the platform components, such as processors and\r\nshared or private memories. The method is applied to model single processor and multiprocessor platforms. Experimental results\r\ndemonstrate an average accuracy of 96% in comparison with the respective measures assessed from the real hardware platform....
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